Overview 

The ACE_FK_701189 is a high-performance hardware solver designed for the real-time execution of Forward Kinematics (FK) and Jacobian Velocity Projections for 6-Degree-of-Freedom (6-DOF) robotic manipulators.

The core provides a dedicated, silicon-optimized path for complex matrix chain multiplications and trigonometric expansions. By offloading these tasks from the primary system processor, it delivers the deterministic, low-latency performance required for high-precision motion control, collision avoidance, and safety-critical monitoring.

Beyond raw computational throughput, the ACE701189 addresses a fundamental challenge in modern robotics: maintaining stable, high‑frequency control loops under strict timing constraints. 

Software‑based FK and Jacobian evaluation introduce jitter, variable execution time, and heavy CPU load, all of which degrade motion quality and complicate safety certification. 

By moving these operations into deterministic hardware, the ACE701189 ensures consistent cycle‑to‑cycle behavior, enabling tighter servo loops, predictable latency budgets, and reliable operation even in multi‑arm or safety‑critical environments. 

Key Characteristics 

• Dual-Stage Compute Pipeline: Integrates high-speed joint trigonometry with an IEEE-754 Single-Precision engine for full analytical coordinate and velocity resolution.

• Guaranteed Determinism: Fixed execution of 623 clock cycles (3115ns @ 200MHz), eliminating jitter and software interrupt latencies.

• Minimal Resource Impact: High computational density requiring only ~4K LUTs and 6 DSP slices (Artix-7 100T), enabling multi-core deployments on a single chip.

• Hardware-Level IP Protection: Native integration with the silicon DNA_PORT for secure node-locking and bitstream protection.

• Precision Verified: Bit-perfect alignment with double-precision reference models (Absolute Error <1e-6). 

Simplified System Integration 

The ACE701189 is designed for "Plug-and-Play" integration into modern SoC and FPGA architectures:

• Standard Interface: Utilizes a single AXI BRAM interface. From the user's perspective, the core is simply a memory-mapped peripheral.

• Asynchronous Domain Decoupling: Supports independent clocking for the User Interface and the Compute Core. Users can drive the I/O at their system frequency (e.g., 100 -160MHz) while the engine runs at a dedicated 200MHz for maximum throughput.

Transparent CDC Management: Internal hardware manages all Clock Domain Crossing and memory arbitration, ensuring data integrity without requiring external synchronizers. 

The ACE_FK architecture is modular and can be tailored by our engineering team to meet specific application requirements:

• Algorithmic Scaling: Capability to add Jacobian Inversion, Inverse Kinematics (IK), or dynamic compensation modules.

• Resource Optimization: Can be stripped down to position-only solving to reduce footprint and latency further.

• Cross-Platform Portability: Logic is designed for portability across Xilinx, Intel, Lattice, and Microchip FPGA families.

Bespoke Equations: Support for custom DH configurations or non-standard analytical models. 

Application 

The ACE701189 core is engineered for high‑precision robotic manipulation where deterministic timing, safety‑critical behavior, and computational efficiency are non‑negotiable.

By offloading all trigonometric, matrix‑chain, and Jacobian computations into dedicated silicon, the core eliminates the latency jitter and CPU load associated with software‑based kinematics. This enables tighter control loops, higher servo update rates, and more stable motion profiles, even in complex multi‑axis systems. 

Key Application Benefits 

Deterministic Control for Safety‑Critical Systems  

The fixed 623‑cycle execution time provides a hard temporal guarantee, simplifying certification paths in industrial, medical, and defense robotics.

Massive CPU Offload for Real‑Time Processors  

The core removes the need for 12 trig evaluations, six 4×4 matrix multiplications, and full Jacobian assembly per cycle. This frees the host processor for higher‑level planning, perception, or safety logic.

Smooth, High‑Bandwidth Motion Control  

With a refresh rate above 320 kHz, the solver supports ultra‑responsive servo loops, enabling smoother trajectories, reduced vibration, and improved end‑effector accuracy.

Multi‑Arm Scalability  

The design is fully stateless. A single FPGA can host multiple FK/Jacobian engines, allowing coordinated control of several robotic arms without increasing processor load.

Seamless Integration with Embedded Architectures  

The AXI‑BRAM interface presents the core as a simple memory‑mapped peripheral. Both hard and soft processors can drive it without custom buses, DMA engines, or synchronization logic.

Certification‑Friendly Determinism  

The unrolled analytical pipeline avoids iterative solvers and branching logic, providing predictable behavior even near singularities—an essential property for systems requiring formal verification.

Typical Use Cases 

• Industrial 6‑axis manipulators

• Collaborative robots (cobots) with strict safety envelopes

• Medical and surgical robotic arms

• Aerospace and defense robotic actuation

• High‑speed pick‑and‑place systems

• Research platforms requiring precise Jacobian‑based control

Algorithm 

The ACE701189 executes a multi-stage analytical routine to resolve the non-linear equations governing 6-axis robotic motion. The engine is designed to perform parallel execution of trigonometric expansions and matrix transformations, maintaining bit-perfect consistency with the Denavit-Hartenberg (DH) model. 

The core decomposes the kinematic problem into four primary computational phases:

1. Joint Trigonometry Resolution: Simultaneous resolution of sine and cosine components for all six joint angles (q_1...q_6). This stage utilizes high-speed CORDIC primitives to ensure maximum precision before entering the floating-point pipeline.

2. Format Translation & Injection:
   Real-time conversion of fixed-point trigonometric results into IEEE-754 Single-Precision format. This ensures that the subsequent matrix operations maintain the high dynamic range required for precision robotics.

3. Forward Kinematic Chain Multiplication:
   The engine solves the recursive transformation chain . It calculates the global radial and vertical projections, ultimately resolving the Cartesian hand position (P_x, P_y, P_z).

4. Jacobian Velocity Projection:
   The solver simultaneously calculates partial derivatives (Jacobian coefficients) to project joint velocities into linear and angular velocities in the task space.

By utilizing this core, the host system avoids the following computational overhead per cycle:

• Trig Functions: 12 simultaneous sine/cosine operations.

• Matrix Math: Chain multiplication of six 4x4 homogenous transformation matrices.

• Differential Geometry: Calculation of the 6x6 Velocity Jacobian matrix.

Format Overhead: All floating-point management and rounding logic are handled in hardware. 

Detailed equations 

To ensure correct integration with the ACE core, the following conventions are utilized:

• Link Lengths (An): Horizontal offsets between joint axes (e.g., A2 is shoulder-to-elbow).

• Link Offsets (Dn): Vertical offsets along joint axes (e.g., D1 is base height, D6 is tool extension).

• Joint Angles (qn): Angular position. The core expects scaled Q2.30 fixed-point values for CORDIC processing.

• Joint Rates (qn_d): Angular velocity in rad/s (FP32).

1. Composite Trigonometry (Primary Chain)

The core calculates the forearm orientation using sum-of-products to maintain pipeline integrity:

c23 = (cos(q2) * cos(q3)) - (sin(q2) * sin(q3)) s23 = (sin(q2) * cos(q3)) + (cos(q2) * sin(q3))

2. Wrist Center & Tool Decoupling (D6 Offset)

The ACE Standard Core treats the tool offset as a 3D extension (dr, dt, dz) relative to the wrist center (rw, zw). This "Decoupler" logic ensures the tool tip is accurately tracked even when rotated by q4:

• rw = (A2 * cos(q2)) + (A3 * c23) + (D4 * s23) 

• zw = D1 + (A2 * sin(q2)) + (A3 * s23) - (D4 * c23)

The Decoupler Constants:

• dr = D6 * cos(q4) * sin(q5) (Radial Extension) 

• dt = D6 * sin(q4) * sin(q5) (Tangential Extension) 

• dz = D6 * cos(q5) (Vertical Extension)

3. Cartesian Position Outputs

Final world-space coordinates account for the tangential shift (dt) introduced by the spherical wrist:

• r_total = rw + (c23 * dr) + (s23 * dz)

• PX = (cos(q1) * r_total) - (sin(q1) * dt)

• PY = (sin(q1) * r_total) + (cos(q1) * dt) 

• PZ = zw + (s23 * dr) - (c23 * dz)

4. Jacobian Producers (Linear Velocity Coefficients)

Linear velocity is synthesized using planar differential components (diff_p, diff_v) computed in parallel:

diff_p = (-sin(s23) * dr) + (c23 * dz) diff_v = (c23 * dr) + (s23 * dz)

• Shoulder (q2) & Elbow (q3): Computed via planar projection logic (BRAM indices 45-50).

• Wrist (q4, q5): Computed as tangential and pitching contributions (BRAM indices 51-56).

5. Velocity Projection (Cartesian & Angular)

The final velocity vector in world space is the sum of joint rates (qn_d) multiplied by their respective coefficients.

Linear Velocity (vx, vy, vz): 

• vx = (-PY * q1_d) + (jv01 * q2_d) + (jv02 * q3_d) + (jv04 * q4_d) + (jv05 * q5_d) 

• vy = (PX * q1_d) + (jv11 * q2_d) + (jv12 * q3_d) + (jv14 * q4_d) + (jv15 * q5_d) 

• vz = (jv21 * q2_d) + (jv22 * q3_d) + (jv24 * q4_d) + (jv25 * q5_d)

Angular Velocity (wx, wy, wz) - Standard R-P-R Convention: 

• wx = (sin(q1) * q2_d) + (sin(q1) * q3_d) + (cos(q1) * c23 * q4_d) + ((sin(q1)*sin(q4) - cos(q1)s23cos(q4)) * q5_d) 

• wy = (-cos(q1) * q2_d) + (-cos(q1) * q3_d) + (sin(q1) * c23 * q4_d) + ((-cos(q1)*sin(q4) - sin(q1)s23cos(q4)) * q5_d) 

• wz = q1_d + (s23 * q4_d) + (c23 * cos(q4) * q5_d) + q6_d

Angles definition 

In this section the variation of the angles q1, q2, q3, q4 and q5 are illustrated by comparing the arm in a starting position and then varying one angle per time by 45 degrees. For q6 no image is generated, since q6 represents the tool rotation around its own axis. 

Technical Characteristics 

This section outlines the physical implementation results of the ACE_FK_701189 core. The core is optimized for the AMD/Xilinx 7-Series architecture but maintains high portability for other FPGA fabrics. 

Resource Utilization

The core is engineered for maximum computational density. The following data represents the core minimalist footprint on a Xilinx Artix-7 100T (csg324-1) device. 

Slice LUTs: 4,008 used out of 63,400 available (6.32% utilization)

Slice Registers: 4,508 used out of 126,800 available (3.56% utilization)

DSP48E1 Slices: 6 used out of 240 available (2.50% utilization)

Block RAM (36Kb): 3 used out of 135 available (2.22% utilization)

Clocking & Timing Closure 

The architecture is designed with high timing slack to ensure easy integration into congested user designs.

• Deterministic Timing Closure: The core comfortably meets a 200 MHz target on -1 speed grade silicon.

• Timing Performance: Verified Worst Negative Slack (WNS) of 0.367 ns at 200 MHz, ensuring stable operation across PVT (Process, Voltage, Temperature) corners in the verification project provided as part of the deliverables.

Zero Failing Endpoints: The design is fully constrained and verified, requiring no specialized floorplanning for standard deployment. 

Execution Latency & Throughput 

The solver utilizes a deep, non-iterative pipeline to provide absolute determinism in its response.

• Core Latency: Exactly 623 Clock Cycles from command to result availability (on the B PORT of the BRAM used as user interface).

• Execution Time: 3115 ns (@ 200 MHz Core Clock).

• Maximum Refresh Rate: ~321 kHz.

Jitter-Free Performance: Because the analytical path is unrolled, the latency remains constant regardless of joint angles or singularity proximity, providing a rock-solid temporal guarantee for control law stability. 

Clock Domain Crossing (CDC) Integrity 

The core features a native asynchronous bridge between the User I/O and the Compute Core:

• Interface Domain: The choice to use a BRAM as interface leaves the user the possibility to use a clock frequency of choice

• Compute Domain: 200 MHz (Optimized for maximum math throughput).

• Security Domain: 50 MHz (Limited by the DNA primitive maximum speed)

Integrity: All inter-clock paths are hardware-interlocked to prevent metastability and data collisions during simultaneous memory access. 

Interfaces and operation flow 

The ACE701189 core is packaged as an AMD IP core. The picture below shows the block used in its verification project. 

The core is managed entirely via read/write operations on a BRAM with AXI interface. The instantiated BRAM is a True Dual Port with port A available to the user and port B managed by the internal Math Engine.

The BRAM has a width of 32 bits and a  depth of 2048 locations. The core only uses the first 64 locations, with the remaining ones completely available for the user via port A (port B is assigned to the internal Math Engine).

The memory Map is reported below:

In addition to the BRAM interface, the core exposes two clock slave interfaces:

• CLK_SLOW is used for the access to the DNA reader primitive (max frequency 100MHz, suggested frequency 50MHz)

• CLK_FAST is used to drive the internal computation engine (max frequency 200MHz)

At start up, the core automatically performs an initialization that lasts (with CLK_SLOW @ 50 MHz and CLK_FAST @ 200MHz) less than 5000 ns. 

When the initialization is complete, the BRAM is populated with the DNA of the FPGA (addresses 53 and 54 with MSB and LSB respectively).

Once the initialization is complete, the user may load the BRAM in accordance with the input reported in the  memory map and,finally, set the START_CMD to 0x1.

The results are written in BRAM, in accordance with the memory map, after the specified latency. The end of execution is communicated by the core by setting the START_CMD to 0x0.

When the START_CMD is asserted, the core performs the entire computation, without possibility to be stopped. Writing on the BRAM addresses 1 to 63 during the execution might compromise the final results and it is, therefore, deprecated, however, regardless of any data corruption, the core terminates its execution in the specified time frame  

Note: if the USER_KEY is not correct, the core terminates in the specified timeframe, but produces unpredictable results. 

Licensing & Ordering Information

The ACE_FK_701189 is delivered as a pre‑packaged Vivado IP core, ready for integration through the AMD/Xilinx IP Catalog. The core is provided as an encrypted, implementation‑ready DCP‑based IP, bound to the FPGA’s silicon DNA identifier to ensure secure deployment.

Each licensed core includes:

• Pre‑packaged Vivado IP (compatible with IP Catalog) including simulation model

• Memory map documentation (available in this datasheet)

• USER_KEY file for license activation

• Example project for rapid integration

ACE provides a USER_KEY value (64 bits) for FPGA Serial Number (DNA for AMD/Xilinx 7 Series).

The keys are delivered in a simple csv file (a template is reported below):

The user may store the file with all the SN/licenses and select the key to load after reading the SN of the FPGA from the BRAM_PORTA interface of the ACE701189 core.

The envisioned process is the following:

1. The file with the keys is embedded the customer software

2. The customer software, waiting at least 5000 ns from power on, reads the FPGA SN from the BRAM_PORTA interface exposed by the  ACE701189 core (addresses 57 and 58).

3. The customer software retrieves the USER_KEY corresponding to the FPGA SN in the ACE provided USER_KEY file.

4. The customer software loads the USER_KEY via the BRAM_PORTA interface exposed by the  ACE701189 core (addresses 59 and 60).

The keys are generated on customer order.

In simulation, a demo DNA is used and the corresponding USER_KEY is provided in the file for a seamless experience.

Pricing 

Pricing is provided directly by ACE based on:

• Deployment volume

• License type

• Optional customization requirements

• Target FPGA family

Customers may request a quotation by providing their expected deployment profile and FPGA device list.

Results 

The ACE701189 has been tested with random input against a double precision model implementing the same equations.

The Matlab function used as golden model is the following:

The results, showing errors below 1e-5 in all cases, of the verification are reported below: