Overview 

The ACE901003 is a high-velocity, deterministic hardware accelerator engineered for the real-time execution of a Damped Pseudo-Inverse Solver 3x6 . Optimized for kinematically redundant systems, the core provides a production-ready "Math-to-Silicon" architecture that transforms complex differential kinematics and regularized matrix inversions into high-frequency, bit-perfect FPGA logic.

By executing a fully unrolled Damped Least-Squares (DLS) sequence—spanning parallelized Normal Equation construction, Cholesky Factorization, Forward/Backward substitution, and Configuration Space Back-Projection—the core resolves non-square matrix mappings in a single, deterministic pipeline pass. This offloads recursive mathematical kernels from a system’s primary processor, providing extreme computational throughput with zero execution jitter.

The integration of an adjustable scalar damping factor (λ2) provides numerical stabilization, ensuring robust behavior even when the underlying physical system approaches mathematical singularities. The core is engineered as a universal mathematical fabric for high-stakes, real-time automation and tracking environments. It is specifically optimized for:

• Kinematically Redundant Robotic Arms (6-DoF Position Control): For robotic manipulators utilizing 6 joints to position an end-effector in 3D task space (x, y, z), the core serves as an ultra-fast inverse kinematics engine. The 3x6 analytical mapping calculates joint velocity corrections from task space velocity targets. The built-in damping ensures smooth trajectory tracking and prevents joint acceleration explosions near kinematic singularities, which is vital for safe human-robot collaboration (cobots) and surgical robotics. For a full FK-IK core, the ACE901003 can be used in combination with the ACE701189 (Forward Kinematic and Jacobian).

• Redundant Autonomous Underwater Vehicles (AUVs) and Over-Actuated Drones: Autonomous vehicles equipped with redundant thruster or control surface configurations (6 independent actuators governing 3 translational degrees of freedom) use this mathematical framework for precise thrust allocation. The hardware core calculates optimal actuator forces instantaneously, minimizing energy consumption and handling actuator saturation constraints on power-efficient edge FPGAs.

• Computer Graphics, Animation, and Teleoperation Haptics: Real-time interactive systems use damped pseudo-inverses to solve inverse kinematics for organic characters or multi-joint mechanical rigs matching 3D target coordinates. In haptic teleoperation, the microsecond-grade latency ensures that force-feedback loops run well above 1 kHz, preventing system instability and providing smooth tactile feedback to the human operator.

• Target Tracking and Geolocation in Multi-Sensor Arrays: Direction-of-arrival (DOA) arrays and distributed radar/sonar clusters linearize overdetermined or redundant 3D tracking vectors using Jacobian approximations. The fully unrolled Cholesky pipeline prevents divergence and guarantees deterministic, real-time state updates in high-dynamic tracking scenarios.

The ACE901003 achieves an exceptionally lean resource utilization footprint by utilizing a symmetric lower-triangular mapping for its internal 3x3 operations, enabling dense multi-core instantiation even on budget-friendly FPGA models.

The core is highly optimized for the AMD 7 Series FPGA architecture, but ACE can easily port the design to any customer-selected FPGA fabric or alternative hardware vendor.

While the core is fully functional out of the box, ACE internal development procedures provide the flexibility for customers to seamlessly adapt the block to their custom architecture, including:

• Custom matrix size

•  custom memory map re-allocation

•  adjustable mathematical precision

• Porting to other FPGA families

• core interfaces (e.g., configuring the dual-port BRAM interfaces to be controlled via an AXI BRAM Controller).

In contrast to software‑based implementations, the ACE901003 delivers architectural safeguards that general‑purpose processors cannot provide. By maintaining dedicated math primitives with fixed-cycle execution, it replaces months of low-level mathematical debugging and numerical-stability validation with a ready-to-use, robust mathematical engine. This shortens time-to-deployment, reduces project risk, and offers a clear competitive advantage where precision, small footprint, and strict determinism are non-negotiable.

Key Features 

Absolute Jitter-Free Determinism: There are no conditional branches or state-dependent loops within the mathematical pipeline. The total latency from loading the last input scalar to the assertion of the output data-valid flag is constant to the exact clock cycle.

Lean Structural Footprint: By taking advantage of the analytical symmetry of the 3x3 intermediate space and unrolling the equations explicitly into hardware, the core eliminates the overhead of generalized matrix-inversion state machines. This drastically reduces the consumption of FPGA DSP slices and LUTs.

Numerical Resilience: Combining Levenberg-Marquardt style damping (λ2) with Cholesky factorization (L · LT) provides an inherently superior condition number compared to standard pseudo-inverse methods.

• Deterministic  508 cycles Latency

• Tested Clock Frequency: 200 MHz (timing closed with ample margin)

• More than 350K operations per second at the tested frequency

• Utilization: 5% of the resources on an entry level  xc7a100tcsg324-1

• Portable across FPGA families and vendors.

• BRAM-based control interface

Theory of operation 

The ACE901003 is a deterministic, fully unrolled mathematical pipeline that implements a Damped Least-Squares (DLS) Pseudo-Inverse Solver for a 3x6 underdetermined system (M=3 rows, N=6 columns). Given a 3x6 Jacobian matrix J, a 3-element task-space target vector v, and a scalar damping factor λ2, the core computes the regularized configuration-space correction vector q according to the following analytical optimization form:

q = JT · (J · JT + λ2 · I)-1 · v

The underlying architecture avoids iterative solver loops, branch predictions, or runtime pivot hunting. Instead, it processes data through a deeply pipelined, multi-stage hardware fabric. This guarantees an identical execution time for every computational cycle, regardless of numerical variations or structural singularities in the input data.

Computational Pipeline Architecture

The hardware core breaks down the complex matrix inversion and back-projection problem into five distinct, sequentially chained hardware phases:

1. Dumped Innovation Multiply-Accumulate

2. Cholesky Core

3. Forward Substitution

4. Backward Substitution

5. Back Projection

Dumped Innovation Multiply-Accumulate

The first stage computes the regularized normal equation matrix in the task space:

M = J · JT + λ2 · I

Since the resulting 3x3 matrix M is inherently symmetric, the hardware fabric optimizes resource utilization by only instantiating logic for the 6 unique lower-triangular elements (M00, M10, M11, M20, M21, M22).

• Symmetric Dot Products: Parallelized 6-tap Multiply-Accumulate (MAC) structures compute the vector dot products of J's rows simultaneously.

• On-the-Fly Damping: The scalar damping factor (λ2) is injected directly into the diagonal accumulators (M00, M11, M22), guaranteeing that the matrix remains positive-definite even when the physical system is in a singular configuration.

Fully Unrolled Cholesky Factorization 

Once the matrix M is assembled, it is routed into a dedicated, unrolled Cholesky factorization core. This block decomposes the matrix into a lower triangular matrix L and its conjugate transpose LT.

• Square Root & Division Primitives: The diagonal entries (L00, L11, L22) are resolved using high-speed, pipelined square root primitives. The off-diagonal entries (L10, L20, L21) utilize dedicated hardware dividers to compute the algebraic steps sequentially without stalling the pipeline.

• Singularity Mitigation: Because λ2 bounds the diagonal values away from zero, the square-root and division units are protected from division-by-zero exceptions, preserving numerical stability.

Forward substitution

With the lower triangular matrix L established, the core solves the intermediate vector y from the input target vector v (v = [v0, v1, v2]T) via forward substitution:

• y0 = v0 / L00

• y1 = (v1 - (L10 · y0)) / L11

• y2 = (v2 - ((L20 · y0) + (L21 · y1))) / L22

The internal data path resolves these equations sequentially using highly optimized subtraction and division primitives, ensuring that intermediate values flow directly into Phase 4 without registering dead cycles.

Backward substitution

The core completes the task-space inversion loop by solving for the intermediate weight vector w through backward substitution against the transposed matrix LT:

• w2 = y2 / L22

• w1 = (y1 - (L21 · w2)) / L11

• w0 = (y0 - ((L10 · w1) + (L20 · w2))) / L00

This phase outputs a heavily stabilized weight vector w, effectively scaling down tracking commands that would otherwise cause physical over-saturation or erratic joint movements in singular configurations.

Back projection

In the final phase, the intermediate task-space weight vector w is projected back onto the 6-dimensional configuration space:

q = JT · w

The hardware implements this via six isolated, parallelized 3-tap MAC engines. Each engine concurrently multiplies a column of the original Jacobian matrix J by the 3-element vector w to yield the final, synchronized outputs (q0 to q5).

The ACE901003 core utilizes IEEE-754 Single-Precision (32-bit) floating-point arithmetic. 

The equivalent software implementation is reported below:

Detailed Resource Utilization

The data below are representative of the AMD 7 series architecture. The percentage are relative to the budget friendly xc7a100tcsg324-1 .

• Used CLB LUTs: 2952 (4.66%)

  • LUT as logic: 2858

  • LUT as Shift Registers: 94

• CLB Registers: 4047 (3.19%)

• CARRY4: 378

• F7 Muxes:39 

• F8 Muxes: 1

• CLB Tiles (in the verification project): 1108 (6.99%)

• Used DSP: 5 (2.08%)

• Used BRAM36K: 1 (0.74%) 

• Used BRAM18K: 0 (0.00%)

• DNA PORT: 1

Timing and throughput 

The core runs on two different clocks:

• CLK_FAST with a maximum frequency of 200 MHz

• CLK_SLOW that shall run at 50MHz (phase aligned with CLK_FAST)

CLK_SLOW is used for the ACE901003 initialization, while CLK_FAST is used for all the runtime operations.

In the verification project, the timing was closed with a robust 0.436ns timing margin and with 0 timing violations.

Interfaces and operation flow 

The Damped Pseudo-Inverse Solver 3x6 core is packaged as an AMD IP core. Figure 1 illustrates the verification configuration. 

Figure 1 

The core is fully controlled through read/write operations on a BRAM (optionally accessible via an AXI BRAM_CONTROLLER). The instantiated BRAM is 1 True Dual Port with port A available to the user and port B managed by the internal Math Engine.

The BRAM has a width of 32 bits and a  depth of 1024 locations. The core uses the first 51 locations, with the remaining ones completely available for the user via port(s) A (port(s) B are assigned to the internal Math Engine). Port(s) A operates in the user clock domain; Port(s) B operates in the internal engine clock domain.

The memory Map is reported below:

Memory Map 

In addition to the BRAM interface, the core exposes:

• Two clock slave interfaces:

  • CLK_SLOW is used for the initialization and for the access to the DNA reader primitive ( 50MHz)

  • CLK_FAST is used to drive the internal computation engine (Max Frequency: 200 MHz)

• A BUSY pin that, when set to high, signals when the core is executing the initialization or its main function. 

The core, at power-up, performs an initialization sequence that lasts (with CLK_SLOW @ 50 MHz) less than 5000 ns. 

When the initialization is complete, the BRAM is populated with the DNA of the FPGA (see Memory Map).

Once the initialization is complete, the user may load the BRAM in accordance with the input reported in the Memory Map and,finally, set the START_CMD to 0x1.

The results are written in BRAM, in accordance with the memory map, after exactly 508 clock cycles (2540 ns @ 200 MHz) . The end of execution is communicated by the core by setting the START_CMD to 0x0 (in BRAM) and via the BUSY PIN (BUSY=0 indicates the core is in the IDLE state, ready for the new execution).

When the START_CMD is asserted, the core performs the entire computation. Execution cannot be stopped. Writing on the BRAM first 51 addresses during the execution will produce undefined results and it is not supported. The execution will always complete in the specified 508 clock cycle window. 

Note: if the USER_KEY is not correct, the core terminates in the specified timeframe, but produces unpredictable results.

Results 

To validate the numerical integrity and dynamic range stability of the ACE901003 computing fabric, the hardware engine was subjected to a rigorous, 10-stage hardware-in-the-loop simulation test sweep. The verification manifest intentionally sweeps the input Jacobian matrix (J) and target vectors (v) across diverse operational ranges, forcing the internal regularized pipelines to calculate task-projection corrections (q) under varying conditioning states.

Testing was evaluated against an un-truncated double-precision analytical software baseline model utilizing maximum observed epsilon drift bounds to audit precision degradation. A strict verification threshold was enforced to guarantee algorithmic convergence stability near kinematic singularities and prevent catastrophic cancellation during the unrolled Cholesky decomposition and back-projection phases.

As compiled in the hardware bit-fidelity verification report below, the core achieved 100% numerical equivalence with zero precision breaches across all evaluated operating envelopes. Maximum observed final q epsilon drift was successfully bounded in the sub-fractional micro-signal space, peaking at 8.21256510-7 under peak stress loading near structural boundaries (Stage 10), while nominal tracking bounds routinely converged down to 1.28724910-8drift (Stage 6), demonstrating true bit-perfect mathematical propagation.

Licensing & Ordering Information 

ACE901003 is delivered as a pre‑packaged Vivado IP core, ready for integration through the AMD/Xilinx IP Catalog.

Each licensed core includes:

• Pre‑packaged Vivado IP (compatible with IP Catalog) including simulation model

• Memory map documentation (available in this datasheet)

• USER_KEY file for license activation

• Example project for rapid integration

ACE provides a USER_KEY value (64 bits) for FPGA Serial Number (DNA for AMD/Xilinx).

The keys are delivered in a simple csv file (a template is reported below):

The user may store the file with all the SN/licenses and select the key to load after reading the SN of the FPGA from the BRAM_PORTA interface of the ACE901003 core.

The envisioned process is the following:

1. The file with the keys is embedded the customer software

2. The customer software, waiting at least 5000 ns from power on, reads the FPGA SN from the BRAM_PORTA interface exposed by the  ACE901003 core.

3. The customer software retrieves the USER_KEY corresponding to the FPGA SN in the ACE provided USER_KEY file.

4. The customer software loads the USER_KEY via the BRAM_PORTA interface exposed by the  ACE901003 core.

The keys are generated on customer order.

In simulation, a demo DNA is used and the corresponding USER_KEY is provided in the file for a seamless experience.

Pricing is provided directly by ACE based on:

• Deployment volume

• License type

• Optional customization requirements

• Target FPGA family

Customers may request a quotation by providing their expected deployment profile and FPGA device list.