Concatenated 3x3 Matrix Multiplier- ACE800333
Concatenated 3x3 Matrix Multiplier- ACE800333
Embedded Files
Overview
ACE800333 is an optimized product from Accelerated Computing Engineering that performs a concatenated multiplication of 3x3 matrices.
Intended for the algorithmic workloads requiring FP32 3×3 matrix concatenation , the ACE800333 is developed following the ACE standard development methodology that achieves low resource utilization while maintaining IEEE-754 FP32 accuracy.
Features
Deterministic 266 cycles Latency
Max Clock Frequency: 200 MHz
750K operations per second at the max frequency
Utilization less than 6% on an entry level xazu1eg-sbva484-1-i FPGA (the smallest member of the AMD Ultrascale Family)
Portable across FPGA families and vendors.
BRAM-based control interface
Theory of operation
The core implements a concatenated matrix multiplication engine designed for high-density arithmetic throughput. The primary operation is defined by the following transformation:
D = (A * B) * C
Where A, B and C are 33 matrices.
To support multi-stage verification and nested algorithms, the core also provides access to the intermediate product:
X = A * B
All elements—including input operands, intermediate products, and final results—are defined and operated in the IEEE-754 Single-Precision Floating-Point (FP32) arithmetic format.
Precision: 24-bit significand (including implicit bit).
Dynamic Range: 1.18e‑38 to 3.40e+38
Detailed Resource Utilization
Used CLB LUTs: 1341
LUT as logic: 1312
LUT as Shift Registers: 29
CLB Registers: 1520
CARRY8: 24
F7 Muxes:27
F8 Muxes: 8
CLB Tiles (in the verification project): 261
Used DSP: 3
Used BRAM36K: 1
Used BRAM18K: 0
DNA PORT: 1
Timing
The core runs on two different clocks:
CLK_FAST with a maximum frequency of 200 MHz
CLK_SLOW that shall run at 50MHz (phase aligned with CLK_FAST)
CLK_SLOW is used for the ACE800333 initialization, while CLK_FAST is used for all the runtime operations.
In the verification project, the timing was closed with a robust 2.517 ns timing margin (WNS) and with 0 timing violations.
Interfaces and operation flow
The Concatenated 3x3 Matrix Multiplier core is packaged as an AMD IP core. Figure 1 illustrates the verification configuration.
Figure 1
The core is fully controlled through read/write operations on a BRAM (optionally accessible via an AXI BRAM_CONTROLLER). The instantiated BRAM is 1 True Dual Port with port A available to the user and port B managed by the internal Math Engine.
The BRAM has a width of 32 bits and a depth of 1024 locations. The core uses the first 53 locations, with the remaining ones completely available for the user via port A (port B is assigned to the internal Math Engine). Port A operates in the user clock domain; Port B operates in the internal engine clock domain.
The memory Map is reported below:
Memory Map
In addition to the BRAM interface, the core exposes:
Two clock slave interfaces:
CLK_SLOW is used for the initialization and for the access to the DNA reader primitive ( 50MHz)
CLK_FAST is used to drive the internal computation engine (Max Frequency: 200 MHz)
A BUSY pin that, when set to high, signals when the core is executing the initialization or its main function.
The core, at power-up, performs an initialization sequence that lasts (with CLK_SLOW @ 50 MHz) less than 5000 ns.
When the initialization is complete, the BRAM is populated with the DNA of the FPGA (see Memory Map).
Once the initialization is complete, the user may load the BRAM in accordance with the input reported in the Memory Map and,finally, set the START_CMD to 0x1.
The results are written in BRAM, in accordance with the memory map, after exactly 266 clock cycles. The end of execution is communicated by the core by setting the START_CMD to 0x0 and via the BUSY PIN (BUSY=0 indicates the core is in the IDLE state, ready for the new execution).
When the START_CMD is asserted, the core performs the entire computation. Execution cannot be stopped. Writing on the BRAM first 53 addresses during the execution will produce undefined results and it is not supported. The execution will always complete in the specified 266 clock cycle window.
Note: if the USER_KEY is not correct, the core terminates in the specified timeframe, but produces unpredictable results.
Results and accuracy
The ACE800333 has been tested against a double precision model implementing the same equations.
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STAGE 1 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 6.2945 8.2675 -4.4300] [ -0.7004 -0.1500 -0.6978] [ 3.9610 0.0000 0.0000] [ -8.8464 -48.2896 -15.1291]
[ 8.1158 2.6472 0.9376] * [ -0.1144 -0.9414 0.3173] * [ 0.0000 4.7975 0.0000] = [ -26.3318 -16.4392 -13.8405]
[ -7.4603 -8.0492 9.1501] [ -0.7045 0.3020 0.6422] [ 0.0000 0.0000 3.2787] [ -1.1906 54.9822 27.9619]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -8.8464 -48.2896 -15.1291] [ -8.8464 -48.2896 -15.1291] [ -8.8464 -48.2896 -15.1291]
[ -26.3318 -16.4392 -13.8405] [ -26.3318 -16.4392 -13.8405] [ -26.3318 -16.4392 -13.8405]
[ -1.1906 54.9822 27.9619] [ -1.1906 54.9822 27.9619] [ -1.1906 54.9822 27.9618]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.818437e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
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STAGE 2 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -9.2858 3.5747 -2.1555] [ -0.9301 0.3672 -0.0012] [ 0.1722 0.0000 0.0000] [ 1.5972 -3.9711 -7.2336]
[ 6.9826 5.1548 3.1096] * [ -0.0419 -0.1095 -0.9931] * [ 0.0000 2.1937 0.0000] = [ -1.3512 -1.9137 -9.0871]
[ 8.6799 4.8626 -6.5763] [ -0.3648 -0.9237 0.1172] [ 0.0000 0.0000 1.9078] [ -1.0124 19.1500 -10.7033]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 1.5972 -3.9711 -7.2336] [ 1.5972 -3.9711 -7.2336] [ 1.5972 -3.9711 -7.2336]
[ -1.3512 -1.9137 -9.0871] [ -1.3512 -1.9137 -9.0871] [ -1.3512 -1.9137 -9.0871]
[ -1.0124 19.1500 -10.7033] [ -1.0124 19.1500 -10.7033] [ -1.0124 19.1500 -10.7033]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 4.866350e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 3 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.3103 -0.2047 4.1873] [ -0.7096 0.3260 0.6247] [ 3.7563 0.0000 0.0000] [ -16.2982 -2.7824 11.9170]
[ 5.9040 -1.0883 5.0937] * [ -0.6839 -0.1050 -0.7220] * [ 0.0000 1.2755 0.0000] = [ -16.1888 -3.5034 15.1511]
[ -6.2625 2.9263 -4.4795] [ -0.1698 -0.9395 0.2975] [ 0.0000 0.0000 2.5298] [ 12.0312 2.3721 -18.6126]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -16.2982 -2.7824 11.9170] [ -16.2982 -2.7824 11.9170] [ -16.2982 -2.7824 11.9170]
[ -16.1888 -3.5034 15.1511] [ -16.1888 -3.5034 15.1511] [ -16.1888 -3.5034 15.1511]
[ 12.0312 2.3721 -18.6126] [ 12.0312 2.3721 -18.6126] [ 12.0312 2.3721 -18.6126]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.473127e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 4 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 3.9815 0.9443 -4.8498] [ -0.6466 -0.3992 -0.6500] [ 4.1541 0.0000 0.0000] [ 3.4132 -14.4033 -10.7738]
[ 7.8181 -7.2275 6.8143] * [ -0.1934 -0.7385 0.6459] * [ 0.0000 2.9263 0.0000] = [ -36.0825 17.3214 -19.3016]
[ 9.1858 -7.0141 -4.9144] [ -0.7379 0.5433 0.4003] [ 0.0000 0.0000 2.7486] [ -3.9751 -3.3863 -34.2722]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 3.4132 -14.4033 -10.7738] [ 3.4132 -14.4033 -10.7738] [ 3.4132 -14.4033 -10.7738]
[ -36.0825 17.3214 -19.3016] [ -36.0825 17.3214 -19.3016] [ -36.0825 17.3214 -19.3016]
[ -3.9751 -3.3863 -34.2722] [ -3.9751 -3.3863 -34.2722] [ -3.9751 -3.3863 -34.2722]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 3.746236e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 5 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 8.3439 5.0746 -8.4829] [ -0.6370 0.7220 0.2701] [ 1.5561 0.0000 0.0000] [ -12.8976 18.2665 -5.9063]
[ -4.2832 -2.3911 -8.9210] * [ -0.7635 -0.5426 -0.3501] * [ 0.0000 2.6427 0.0000] = [ 8.5605 5.3758 -6.8921]
[ 5.1440 1.3564 0.6160] [ -0.1062 -0.4293 0.8969] [ 0.0000 0.0000 0.8282] [ -6.8119 7.1713 1.2151]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -12.8976 18.2665 -5.9063] [ -12.8976 18.2665 -5.9063] [ -12.8976 18.2665 -5.9063]
[ 8.5605 5.3758 -6.8921] [ 8.5605 5.3758 -6.8921] [ 8.5605 5.3758 -6.8921]
[ -6.8119 7.1713 1.2151] [ -6.8119 7.1713 1.2151] [ -6.8119 7.1713 1.2151]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 5.099505e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 6 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 2.0396 3.7843 -8.3236] [ -0.1528 0.9328 -0.3265] [ 3.8746 0.0000 0.0000] [ 4.0591 -3.6187 -40.2519]
[ -4.7406 4.9630 -5.4205] * [ -0.8279 -0.3012 -0.4732] * [ 0.0000 4.0865 0.0000] = [ -1.7795 -28.5651 -22.7416]
[ 3.0816 -0.9892 8.2667] [ -0.5397 0.1980 0.8182] [ 0.0000 0.0000 4.3435] [ -15.9373 19.6533 27.0431]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 4.0591 -3.6187 -40.2519] [ 4.0591 -3.6187 -40.2519] [ 4.0591 -3.6187 -40.2519]
[ -1.7795 -28.5651 -22.7416] [ -1.7795 -28.5651 -22.7416] [ -1.7795 -28.5651 -22.7416]
[ -15.9373 19.6533 27.0431] [ -15.9373 19.6533 27.0431] [ -15.9373 19.6533 27.0431]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.520391e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 7 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -8.3113 6.0014 -6.3631] [ -0.1291 0.5922 -0.7954] [ 2.0090 0.0000 0.0000] [ -0.7576 -4.5396 1.9333]
[ -2.0043 -1.3717 -4.7239] * [ -0.8250 -0.5092 -0.2452] * [ 0.0000 0.3798 0.0000] = [ 8.0151 -1.3062 -0.8256]
[ -4.8026 8.2130 -7.0892] [ -0.5502 0.6245 0.5543] [ 0.0000 0.0000 1.1996] [ -4.5309 -4.3503 -2.5476]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -0.7576 -4.5396 1.9333] [ -0.7576 -4.5396 1.9333] [ -0.7576 -4.5396 1.9333]
[ 8.0151 -1.3062 -0.8256] [ 8.0151 -1.3062 -0.8256] [ 8.0151 -1.3062 -0.8256]
[ -4.5309 -4.3503 -2.5476] [ -4.5309 -4.3503 -2.5476] [ -4.5309 -4.3503 -2.5476]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 4.912997e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 8 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -7.5336 -1.6547 8.8957] [ -0.3279 0.8895 0.3181] [ 0.6599 0.0000 0.0000] [ 0.4798 -48.2979 27.4458]
[ -6.3218 -9.0069 -0.1827] * [ -0.8740 -0.1579 -0.4595] * [ 0.0000 4.7103 0.0000] = [ 6.6058 -19.4204 9.4504]
[ -5.2009 8.0543 -0.2149] [ -0.3586 -0.4287 0.8292] [ 0.0000 0.0000 4.7807] [ -3.4688 -27.3483 -26.4553]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 0.4798 -48.2979 27.4458] [ 0.4798 -48.2979 27.4458] [ 0.4798 -48.2979 27.4458]
[ 6.6058 -19.4204 9.4504] [ 6.6058 -19.4204 9.4504] [ 6.6058 -19.4204 9.4504]
[ -3.4688 -27.3483 -26.4553] [ -3.4688 -27.3483 -26.4553] [ -3.4688 -27.3483 -26.4553]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 3.806215e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 9 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 1.5042 -2.9368 -9.1395] [ -0.6799 -0.0881 -0.7280] [ 1.8424 0.0000 0.0000] [ 8.4274 -20.4477 -21.6386]
[ -8.8044 6.4239 -6.6202] * [ -0.6019 -0.5002 0.6226] * [ 0.0000 3.1281 0.0000] = [ 9.0157 -25.4632 33.1948]
[ -5.3044 -9.6919 2.9823] [ -0.4190 0.8614 0.2870] [ 0.0000 0.0000 3.9011] [ 15.0893 24.6617 -5.1354]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 8.4274 -20.4477 -21.6386] [ 8.4274 -20.4477 -21.6386] [ 8.4274 -20.4477 -21.6386]
[ 9.0157 -25.4632 33.1948] [ 9.0157 -25.4632 33.1948] [ 9.0157 -25.4632 33.1948]
[ 15.0893 24.6617 -5.1354] [ 15.0893 24.6617 -5.1354] [ 15.0893 24.6617 -5.1354]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.408645e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 10 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -8.3775 -0.2642 -3.8730] [ -0.6243 0.7449 -0.2355] [ 2.7508 0.0000 0.0000] [ 20.0681 -17.1901 -3.6237]
[ 8.5877 -1.2828 0.1702] * [ -0.6069 -0.6522 -0.4542] * [ 0.0000 3.1124 0.0000] = [ -12.8358 22.4384 -3.7975]
[ 5.5143 -1.0643 0.2154] [ -0.4919 -0.1406 0.8592] [ 0.0000 0.0000 2.9352] [ -7.9840 14.8499 -1.8499]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 20.0681 -17.1901 -3.6237] [ 20.0681 -17.1901 -3.6237] [ 20.0681 -17.1901 -3.6237]
[ -12.8358 22.4384 -3.7975] [ -12.8358 22.4384 -3.7975] [ -12.8358 22.4384 -3.7975]
[ -7.9840 14.8499 -1.8499] [ -7.9840 14.8499 -1.8499] [ -7.9840 14.8499 -1.8499]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.532734e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 11 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -5.8452 -5.3902 -5.4816] [ -0.4082 0.1473 -0.9009] [ 1.2903 0.0000 0.0000] [ 11.2249 5.9437 8.9886]
[ -3.9751 6.8862 -6.5858] * [ -0.2915 -0.9563 -0.0243] * [ 0.0000 2.0436 0.0000] = [ 6.8555 -18.0546 1.6668]
[ -0.5815 -6.1047 -5.4467] [ -0.8651 0.2527 0.4333] [ 0.0000 0.0000 2.9745] [ 8.6822 8.9425 -5.0203]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 11.2249 5.9437 8.9886] [ 11.2249 5.9437 8.9886] [ 11.2249 5.9437 8.9886]
[ 6.8555 -18.0546 1.6668] [ 6.8555 -18.0546 1.6668] [ 6.8555 -18.0546 1.6668]
[ 8.6822 8.9425 -5.0203] [ 8.6822 8.9425 -5.0203] [ 8.6822 8.9425 -5.0203]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.243691e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 12 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -4.7558 -5.5651 -3.6244] [ -0.1009 0.1059 -0.9892] [ 2.2942 0.0000 0.0000] [ 12.9183 17.7589 12.6529]
[ 2.0569 -7.6516 -1.5167] * [ -0.3098 -0.9482 -0.0699] * [ 0.0000 4.8154 0.0000] = [ 8.2520 33.8009 -4.6329]
[ 4.2243 -4.0665 0.1572] [ -0.9454 0.2994 0.1285] [ 0.0000 0.0000 2.7340] [ 1.5712 20.9497 -10.5923]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 12.9183 17.7589 12.6529] [ 12.9183 17.7589 12.6529] [ 12.9183 17.7589 12.6529]
[ 8.2520 33.8009 -4.6329] [ 8.2520 33.8009 -4.6329] [ 8.2520 33.8009 -4.6329]
[ 1.5712 20.9497 -10.5923] [ 1.5712 20.9497 -10.5923] [ 1.5712 20.9497 -10.5923]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.819008e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 13 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 0.4227 2.4812 -2.6513] [ -0.5899 0.7268 0.3518] [ 0.5338 0.0000 0.0000] [ -0.1883 5.9499 -7.7849]
[ -5.3681 3.5827 9.7596] * [ -0.6087 -0.1140 -0.7852] * [ 0.0000 3.2688 0.0000] = [ -2.2380 -35.6960 0.6720]
[ -0.2220 -2.0897 -9.2452] [ -0.5306 -0.6773 0.5096] [ 0.0000 0.0000 2.4709] [ 3.3675 20.7199 -7.7799]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -0.1883 5.9499 -7.7849] [ -0.1883 5.9499 -7.7849] [ -0.1883 5.9499 -7.7849]
[ -2.2380 -35.6960 0.6720] [ -2.2380 -35.6960 0.6720] [ -2.2380 -35.6960 0.6720]
[ 3.3675 20.7199 -7.7799] [ 3.3675 20.7199 -7.7799] [ 3.3675 20.7199 -7.7799]
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LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.355111e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 14 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
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MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.5810 7.8184 -6.0438] [ -0.4387 -0.4710 -0.7653] [ 1.1997 0.0000 0.0000] [ -1.1315 -50.1235 0.0297]
[ 4.3007 -3.3167 -9.3892] * [ -0.4211 -0.6446 0.6381] * [ 0.0000 4.4326 0.0000] = [ 8.3536 -24.5646 -0.8891]
[ 8.0744 3.9749 4.8815] [ -0.7938 0.6022 0.0845] [ 0.0000 0.0000 0.1434] [ -10.9067 -15.1822 -0.4632]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -1.1315 -50.1235 0.0297] [ -1.1315 -50.1235 0.0297] [ -1.1315 -50.1235 0.0297]
[ 8.3536 -24.5646 -0.8891] [ 8.3536 -24.5646 -0.8891] [ 8.3536 -24.5646 -0.8891]
[ -10.9067 -15.1822 -0.4632] [ -10.9067 -15.1822 -0.4632] [ -10.9067 -15.1822 -0.4632]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 4.852695e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 15 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -0.2020 4.2539 -8.8076] [ -0.1335 0.7670 -0.6276] [ 4.8649 0.0000 0.0000] [ -12.2923 -20.7554 -27.8438]
[ -6.6415 0.0094 3.6394] * [ -0.9744 -0.2170 -0.0580] * [ 0.0000 3.2450 0.0000] = [ 1.0681 -9.4060 27.9842]
[ 9.5736 -0.5782 -9.1514] [ -0.1807 0.6038 0.7764] [ 0.0000 0.0000 4.0017] [ 4.5698 6.3048 -52.3404]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -12.2923 -20.7554 -27.8438] [ -12.2923 -20.7554 -27.8438] [ -12.2923 -20.7554 -27.8438]
[ 1.0681 -9.4060 27.9842] [ 1.0681 -9.4060 27.9842] [ 1.0681 -9.4060 27.9842]
[ 4.5698 6.3048 -52.3404] [ 4.5698 6.3048 -52.3404] [ 4.5698 6.3048 -52.3404]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.706113e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 16 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -0.9240 -8.3306 -2.1812] [ -0.0911 0.9139 0.3955] [ 4.9203 0.0000 0.0000] [ 33.5855 -1.9996 2.5300]
[ -1.3522 -7.3366 6.6276] * [ -0.6015 0.2661 -0.7533] * [ 0.0000 0.8358 0.0000] = [ -3.5650 -4.3623 4.5006]
[ 6.5063 -6.5322 6.0673] [ -0.7937 -0.3065 0.5255] [ 0.0000 0.0000 0.5311] [ -7.2795 1.9632 5.6731]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 33.5855 -1.9996 2.5300] [ 33.5855 -1.9996 2.5300] [ 33.5855 -1.9996 2.5300]
[ -3.5650 -4.3623 4.5006] [ -3.5650 -4.3623 4.5006] [ -3.5650 -4.3623 4.5006]
[ -7.2795 1.9632 5.6731] [ -7.2795 1.9632 5.6731] [ -7.2795 1.9632 5.6731]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.999210e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 17 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -2.5518 -3.2101 -8.9465] [ -0.3616 -0.1536 -0.9196] [ 3.4905 0.0000 0.0000] [ 33.6428 -6.2025 -0.6267]
[ -6.0376 9.0326 4.7572] * [ -0.4685 -0.8229 0.3216] * [ 0.0000 3.3326 0.0000] = [ -20.5360 -13.0060 8.4883]
[ -0.2062 8.4066 -4.6176] [ -0.8061 0.5471 0.2256] [ 0.0000 0.0000 0.8907] [ -0.4935 -31.3670 1.6494]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 33.6428 -6.2025 -0.6267] [ 33.6428 -6.2025 -0.6267] [ 33.6428 -6.2025 -0.6267]
[ -20.5360 -13.0060 8.4883] [ -20.5360 -13.0060 8.4883] [ -20.5360 -13.0060 8.4883]
[ -0.4935 -31.3670 1.6494] [ -0.4935 -31.3670 1.6494] [ -0.4935 -31.3670 1.6494]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 9.054428e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 18 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -7.4397 -9.3480 3.3835] [ -0.4205 0.7921 -0.4425] [ 0.6031 0.0000 0.0000] [ 6.6464 -1.0379 6.4565]
[ 9.9816 1.2240 -6.1913] * [ -0.8960 -0.4393 0.0652] * [ 0.0000 2.9475 0.0000] = [ -2.6597 13.9833 -11.1675]
[ -6.5776 7.6373 -2.6217] [ -0.1428 0.4239 0.8944] [ 0.0000 0.0000 1.1309] [ -2.2329 -28.5206 1.2027]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 6.6464 -1.0379 6.4565] [ 6.6464 -1.0379 6.4565] [ 6.6464 -1.0379 6.4565]
[ -2.6597 13.9833 -11.1675] [ -2.6597 13.9833 -11.1675] [ -2.6597 13.9833 -11.1675]
[ -2.2329 -28.5206 1.2027] [ -2.2329 -28.5206 1.2027] [ -2.2329 -28.5206 1.2027]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.469386e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 19 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -2.3076 -4.1912 6.4875] [ -0.5011 0.3412 -0.7953] [ 2.1263 0.0000 0.0000] [ 7.8767 9.9386 2.6602]
[ 1.6597 2.3418 9.6533] * [ -0.8510 -0.3610 0.3813] * [ 0.0000 1.5636 0.0000] = [ -9.2291 12.6633 3.3284]
[ -4.9639 -4.6944 4.6050] [ -0.1570 0.8679 0.4713] [ 0.0000 0.0000 0.8074] [ 12.2458 6.2508 3.4946]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 7.8767 9.9386 2.6602] [ 7.8767 9.9386 2.6602] [ 7.8767 9.9386 2.6602]
[ -9.2291 12.6633 3.3284] [ -9.2291 12.6633 3.3284] [ -9.2291 12.6633 3.3284]
[ 12.2458 6.2508 3.4946] [ 12.2458 6.2508 3.4946] [ 12.2458 6.2508 3.4946]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 6.324198e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 20 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -6.4247 1.9705 3.9978] [ -0.1104 0.9851 -0.1321] [ 1.6257 0.0000 0.0000] [ -6.0235 -3.5729 3.9232]
[ -1.5423 -0.5815 2.7706] * [ -0.5126 -0.1703 -0.8416] * [ 0.0000 0.5281 0.0000] = [ -3.0740 -0.7869 6.5503]
[ -8.1154 3.9190 -9.3279] [ -0.8515 -0.0252 0.5238] [ 0.0000 0.0000 3.0548] [ 11.1026 -4.4506 -21.7250]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -6.0235 -3.5729 3.9232] [ -6.0235 -3.5729 3.9232] [ -6.0235 -3.5729 3.9232]
[ -3.0740 -0.7869 6.5503] [ -3.0740 -0.7869 6.5503] [ -3.0740 -0.7869 6.5503]
[ 11.1026 -4.4506 -21.7250] [ 11.1026 -4.4506 -21.7250] [ 11.1026 -4.4506 -21.7250]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.000940e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 21 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.5760 -4.6706 -1.1983] [ -0.6309 -0.0756 -0.7722] [ 3.4757 0.0000 0.0000] [ -3.3337 0.9778 -8.5601]
[ -1.5309 -6.9269 0.5429] * [ -0.3734 -0.8428 0.3876] * [ 0.0000 0.3400 0.0000] = [ 11.0633 2.1224 -1.5663]
[ -8.1835 -4.3799 -0.8515] [ -0.6801 0.5329 0.5035] [ 0.0000 0.0000 1.2740] [ 25.6422 1.3111 5.3411]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -3.3337 0.9778 -8.5601] [ -3.3337 0.9778 -8.5601] [ -3.3337 0.9778 -8.5601]
[ 11.0633 2.1224 -1.5663] [ 11.0633 2.1224 -1.5663] [ 11.0633 2.1224 -1.5663]
[ 25.6422 1.3111 5.3411] [ 25.6422 1.3111 5.3411] [ 25.6422 1.3111 5.3411]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 4.097116e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 22 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -5.5192 -3.1108 -9.8657] [ -0.8927 0.3312 -0.3057] [ 0.1788 0.0000 0.0000] [ 1.6767 5.9288 -7.3009]
[ 3.3567 5.6104 2.0434] * [ -0.0011 -0.6799 -0.7333] * [ 0.0000 0.8794 0.0000] = [ -0.7016 -3.5524 -14.0718]
[ 6.8878 3.5066 -2.2646] [ -0.4507 -0.6543 0.6073] [ 0.0000 0.0000 3.6088] [ -0.9177 1.2123 -21.8411]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 1.6767 5.9288 -7.3009] [ 1.6767 5.9288 -7.3009] [ 1.6767 5.9288 -7.3009]
[ -0.7016 -3.5524 -14.0718] [ -0.7016 -3.5524 -14.0718] [ -0.7016 -3.5524 -14.0718]
[ -0.9177 1.2123 -21.8411] [ -0.9177 1.2123 -21.8411] [ -0.9177 1.2123 -21.8411]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 6.562689e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 23 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -0.5303 2.1478 -5.1430] [ -0.9122 0.4059 -0.0562] [ 3.2381 0.0000 0.0000] [ 5.7081 6.6970 -15.6855]
[ -6.9456 -6.1651 8.3485] * [ -0.2248 -0.6103 -0.7596] * [ 0.0000 3.3951 0.0000] = [ 15.7422 -16.0785 33.3233]
[ -3.1775 4.7685 -4.6188] [ -0.3426 -0.6803 0.6480] [ 0.0000 0.0000 3.1789] [ 11.0380 -3.5922 -20.4614]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 5.7081 6.6970 -15.6855] [ 5.7081 6.6970 -15.6855] [ 5.7081 6.6970 -15.6855]
[ 15.7422 -16.0785 33.3233] [ 15.7422 -16.0785 33.3233] [ 15.7422 -16.0785 33.3233]
[ 11.0380 -3.5922 -20.4614] [ 11.0380 -3.5922 -20.4614] [ 11.0380 -3.5922 -20.4614]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.493270e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 24 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 8.9035 -5.2754 -0.9972] [ -0.7170 0.5759 -0.3928] [ 2.7037 0.0000 0.0000] [ -10.9483 41.2157 -1.8313]
[ -5.8213 -7.6121 -0.8255] * [ -0.3260 -0.7751 -0.5413] * [ 0.0000 4.3497 0.0000] = [ 19.3686 12.0144 7.6699]
[ 4.1856 2.1461 3.2389] [ -0.6162 -0.2600 0.7434] [ 0.0000 0.0000 1.3239] [ -15.4011 -0.4140 -0.5269]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -10.9483 41.2157 -1.8313] [ -10.9483 41.2157 -1.8313] [ -10.9483 41.2157 -1.8313]
[ 19.3686 12.0144 7.6699] [ 19.3686 12.0144 7.6699] [ 19.3686 12.0144 7.6699]
[ -15.4011 -0.4140 -0.5269] [ -15.4011 -0.4140 -0.5269] [ -15.4011 -0.4140 -0.5269]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.661314e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 25 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -3.6385 2.9110 0.8943] [ -0.5404 0.7796 0.3165] [ 1.8291 0.0000 0.0000] [ 0.2931 -11.8299 -11.2691]
[ -7.6157 -0.4107 2.9462] * [ -0.3916 0.0999 -0.9147] * [ 0.0000 3.8175 0.0000] = [ 3.8084 -29.7762 -4.0625]
[ 8.7966 2.7863 0.8777] [ -0.7447 -0.6182 0.2513] [ 0.0000 0.0000 3.1395] [ -11.8861 25.1718 1.4309]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 0.2931 -11.8299 -11.2691] [ 0.2931 -11.8299 -11.2691] [ 0.2931 -11.8299 -11.2691]
[ 3.8084 -29.7762 -4.0625] [ 3.8084 -29.7762 -4.0625] [ 3.8084 -29.7762 -4.0625]
[ -11.8861 25.1718 1.4309] [ -11.8861 25.1718 1.4309] [ -11.8861 25.1717 1.4309]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.294445e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 26 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.4396 -6.1594 -8.1236] [ -0.8096 0.5769 -0.1083] [ 1.3107 0.0000 0.0000] [ 1.8464 2.3493 -16.8069]
[ 8.6571 -7.2225 0.5081] * [ -0.4558 -0.7341 -0.5034] * [ 0.0000 0.2223 0.0000] = [ -5.1175 2.2482 11.8292]
[ 9.4548 3.9253 0.6069] [ -0.3699 -0.3582 0.8573] [ 0.0000 0.0000 3.7747] [ -12.6722 0.5237 -9.3585]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 1.8464 2.3493 -16.8069] [ 1.8464 2.3493 -16.8069] [ 1.8464 2.3493 -16.8069]
[ -5.1175 2.2482 11.8292] [ -5.1175 2.2482 11.8292] [ -5.1175 2.2482 11.8292]
[ -12.6722 0.5237 -9.3585] [ -12.6722 0.5237 -9.3585] [ -12.6722 0.5237 -9.3585]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 6.358292e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 27 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -5.1443 -2.8154 3.6683] [ -0.0364 0.5687 -0.8218] [ 3.8456 0.0000 0.0000] [ -3.7446 1.4507 27.5263]
[ -1.1520 4.7268 4.0809] * [ -0.6145 -0.6612 -0.4304] * [ 0.0000 1.9840 0.0000] = [ -23.3767 -3.5383 1.7651]
[ 3.7559 -2.1059 -1.1539] [ -0.7881 0.4893 0.3735] [ 0.0000 0.0000 4.0426] [ 7.9482 5.8796 -10.5560]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -3.7446 1.4507 27.5263] [ -3.7446 1.4507 27.5263] [ -3.7446 1.4507 27.5263]
[ -23.3767 -3.5383 1.7651] [ -23.3767 -3.5383 1.7651] [ -23.3766 -3.5383 1.7651]
[ 7.9482 5.8796 -10.5560] [ 7.9482 5.8796 -10.5560] [ 7.9482 5.8796 -10.5560]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.952869e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 28 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.1015 5.8081 3.4253] [ -0.6588 -0.2304 -0.7162] [ 2.0348 0.0000 0.0000] [ -13.6796 -19.0191 2.8709]
[ -2.4521 8.9861 -1.2271] * [ -0.1433 -0.8961 0.4201] * [ 0.0000 3.7435 0.0000] = [ 2.5107 -29.7711 20.0110]
[ -5.6796 -3.4487 6.6700] [ -0.7386 0.3794 0.5573] [ 0.0000 0.0000 4.1279] [ -1.4049 25.9418 26.1536]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -13.6796 -19.0191 2.8709] [ -13.6796 -19.0191 2.8709] [ -13.6796 -19.0191 2.8709]
[ 2.5107 -29.7711 20.0110] [ 2.5107 -29.7711 20.0110] [ 2.5107 -29.7711 20.0110]
[ -1.4049 25.9418 26.1536] [ -1.4049 25.9418 26.1536] [ -1.4049 25.9418 26.1536]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.782607e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 29 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.7993 -8.2010 3.5730] [ -0.9529 0.1918 0.2348] [ 4.3951 0.0000 0.0000] [ -15.7080 0.9087 0.0262]
[ -3.6295 -7.7659 -0.0965] * [ -0.2842 -0.2946 -0.9124] * [ 0.0000 4.9446 0.0000] = [ 24.9445 8.3175 0.0162]
[ 0.6813 -7.2741 -6.2058] [ -0.1058 -0.9362 0.3353] [ 0.0000 0.0000 0.0026] [ 9.1177 39.9693 0.0123]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -15.7080 0.9087 0.0262] [ -15.7080 0.9087 0.0262] [ -15.7080 0.9087 0.0262]
[ 24.9445 8.3175 0.0162] [ 24.9445 8.3175 0.0162] [ 24.9445 8.3175 0.0162]
[ 9.1177 39.9693 0.0123] [ 9.1177 39.9693 0.0123] [ 9.1177 39.9693 0.0123]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.149804e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 30 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 7.3088 0.5536 -5.4431] [ -0.4557 0.5097 -0.7297] [ 3.6488 0.0000 0.0000] [ -1.8734 3.9759 -44.5548]
[ 2.2513 -0.4095 -0.0381] * [ -0.6702 -0.7360 -0.0955] * [ 0.0000 4.4538 0.0000] = [ -2.6605 6.3776 -8.0036]
[ 9.7990 6.0270 8.0170] [ -0.5858 0.4456 0.6770] [ 0.0000 0.0000 4.9115] [ -48.1674 18.3993 -11.2895]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -1.8734 3.9759 -44.5548] [ -1.8734 3.9759 -44.5548] [ -1.8734 3.9759 -44.5548]
[ -2.6605 6.3776 -8.0036] [ -2.6605 6.3776 -8.0036] [ -2.6605 6.3776 -8.0036]
[ -48.1674 18.3993 -11.2895] [ -48.1674 18.3993 -11.2895] [ -48.1674 18.3993 -11.2895]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 9.444569e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 31 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.3806 1.6018 7.2542] [ -0.2425 0.4974 -0.8329] [ 0.6154 0.0000 0.0000] [ -4.6901 5.0745 -0.9463]
[ 1.6289 -9.6603 -0.3141] * [ -0.6396 -0.7275 -0.2482] * [ 0.0000 1.0275 0.0000] = [ 3.7004 7.9012 0.6489]
[ 8.5663 -7.5828 6.8971] [ -0.7295 0.4726 0.4946] [ 0.0000 0.0000 0.7326] [ -1.3900 13.3949 -1.3493]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -4.6901 5.0745 -0.9463] [ -4.6901 5.0745 -0.9463] [ -4.6901 5.0745 -0.9463]
[ 3.7004 7.9012 0.6489] [ 3.7004 7.9012 0.6489] [ 3.7004 7.9012 0.6489]
[ -1.3900 13.3949 -1.3493] [ -1.3900 13.3949 -1.3493] [ -1.3900 13.3949 -1.3493]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 4.571855e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 32 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -6.2186 -4.3627 -0.0177] [ -0.1250 0.9801 0.1545] [ 1.0299 0.0000 0.0000] [ 3.0377 -30.3894 1.1529]
[ -9.1470 0.7719 0.7160] * [ -0.4945 0.0734 -0.8661] * [ 0.0000 4.7397 0.0000] = [ 0.1499 -42.8470 -0.7144]
[ 2.7040 3.9033 -1.0963] [ -0.8602 -0.1846 0.4754] [ 0.0000 0.0000 0.4104] [ -1.3645 14.8784 -1.4297]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 3.0377 -30.3894 1.1529] [ 3.0377 -30.3894 1.1529] [ 3.0377 -30.3894 1.1529]
[ 0.1499 -42.8470 -0.7144] [ 0.1499 -42.8470 -0.7144] [ 0.1499 -42.8470 -0.7144]
[ -1.3645 14.8784 -1.4297] [ -1.3645 14.8784 -1.4297] [ -1.3645 14.8784 -1.4297]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 3.792301e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 33 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -7.8858 2.4192 8.6240] [ -0.0499 0.9930 0.1070] [ 0.6697 0.0000 0.0000] [ -5.0758 -1.3378 14.8025]
[ -7.1592 1.4742 4.5732] * [ -0.6766 0.0452 -0.7350] * [ 0.0000 0.1544 0.0000] = [ -2.6789 -1.1647 5.6931]
[ -6.6708 -8.9584 4.7568] [ -0.7347 -0.1090 0.6696] [ 0.0000 0.0000 4.6957] [ 1.9410 -1.1658 42.5227]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -5.0758 -1.3378 14.8025] [ -5.0758 -1.3378 14.8025] [ -5.0758 -1.3378 14.8025]
[ -2.6789 -1.1647 5.6931] [ -2.6789 -1.1647 5.6931] [ -2.6789 -1.1647 5.6931]
[ 1.9410 -1.1658 42.5227] [ 1.9410 -1.1658 42.5227] [ 1.9410 -1.1658 42.5227]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.004785e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 34 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -3.9739 -0.6586 6.8441] [ -0.6122 0.5981 0.5172] [ 2.6999 0.0000 0.0000] [ 6.2004 -24.5752 15.3646]
[ -4.0893 2.9640 1.1807] * [ -0.7849 -0.3807 -0.4888] * [ 0.0000 3.5346 0.0000] = [ 0.1736 -15.5759 -13.6664]
[ -3.3413 -9.4954 7.0820] [ -0.0955 -0.7053 0.7025] [ 0.0000 0.0000 4.9975] [ 23.8205 -11.9401 39.4231]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 6.2004 -24.5752 15.3646] [ 6.2004 -24.5752 15.3646] [ 6.2004 -24.5752 15.3646]
[ 0.1736 -15.5759 -13.6664] [ 0.1736 -15.5759 -13.6664] [ 0.1736 -15.5759 -13.6664]
[ 23.8205 -11.9401 39.4231] [ 23.8205 -11.9401 39.4231] [ 23.8205 -11.9401 39.4231]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.811626e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 35 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -4.2430 5.2791 -6.4377] [ -0.8091 0.5727 0.1315] [ 3.7277 0.0000 0.0000] [ 9.0869 -7.1502 -24.7476]
[ -1.7095 6.3641 -2.8073] * [ -0.5207 -0.5951 -0.6122] * [ 0.0000 3.6813 0.0000] = [ -4.3463 -11.7201 -17.7254]
[ -0.7032 -7.9956 -8.8659] [ -0.2724 -0.5638 0.7797] [ 0.0000 0.0000 2.8093] [ 26.6420 34.4343 -5.9303]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 9.0869 -7.1502 -24.7476] [ 9.0869 -7.1502 -24.7476] [ 9.0869 -7.1502 -24.7476]
[ -4.3463 -11.7201 -17.7254] [ -4.3463 -11.7201 -17.7254] [ -4.3463 -11.7201 -17.7254]
[ 26.6420 34.4343 -5.9303] [ 26.6420 34.4343 -5.9303] [ 26.6420 34.4343 -5.9303]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 2.886892e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 36 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -6.3161 -7.3175 -8.5709] [ -0.4417 -0.3691 -0.8177] [ 1.6605 0.0000 0.0000] [ 17.5605 10.8645 -0.3992]
[ 1.9442 -5.7480 -5.1503] * [ -0.0133 -0.9087 0.4173] * [ 0.0000 1.4867 0.0000] = [ 6.3726 5.2036 -1.8708]
[ -4.0013 7.8988 -8.9249] [ -0.8971 0.1952 0.3964] [ 0.0000 0.0000 0.3102] [ 16.0545 -11.0649 0.9401]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 17.5605 10.8645 -0.3992] [ 17.5605 10.8645 -0.3992] [ 17.5605 10.8645 -0.3992]
[ 6.3726 5.2036 -1.8708] [ 6.3726 5.2036 -1.8708] [ 6.3726 5.2036 -1.8708]
[ 16.0545 -11.0649 0.9401] [ 16.0545 -11.0649 0.9401] [ 16.0545 -11.0649 0.9401]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.122327e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 37 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ -4.0351 5.2285 -8.3828] [ -0.5395 0.4822 -0.6902] [ 3.0173 0.0000 0.0000] [ 25.9411 -12.4661 -15.2705]
[ -9.0730 2.6214 5.5448] * [ -0.1103 -0.8532 -0.5099] * [ 0.0000 2.6305 0.0000] = [ -0.0677 -20.2939 28.3595]
[ 0.1086 -8.2022 8.1027] [ -0.8347 -0.1989 0.5135] [ 0.0000 0.0000 3.6485] [ -17.8537 14.3053 30.1653]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 25.9411 -12.4661 -15.2705] [ 25.9411 -12.4661 -15.2705] [ 25.9411 -12.4661 -15.2705]
[ -0.0677 -20.2939 28.3595] [ -0.0677 -20.2939 28.3595] [ -0.0677 -20.2939 28.3595]
[ -17.8537 14.3053 30.1653] [ -17.8537 14.3053 30.1653] [ -17.8537 14.3053 30.1653]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.430580e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 38 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 4.1451 3.8506 -8.7682] [ -0.6303 0.4495 0.6330] [ 0.2567 0.0000 0.0000] [ -1.1857 3.0750 -1.7898]
[ 5.6275 1.1334 5.6035] * [ -0.7687 -0.2472 -0.5899] * [ 0.0000 0.3644 0.0000] = [ -1.2904 -0.9333 2.5241]
[ -4.2405 -2.0696 -3.2483] [ -0.1087 -0.8584 0.5013] [ 0.0000 0.0000 0.4426] [ 1.1850 0.5080 -1.3684]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ -1.1857 3.0750 -1.7898] [ -1.1857 3.0750 -1.7898] [ -1.1857 3.0750 -1.7898]
[ -1.2904 -0.9333 2.5241] [ -1.2904 -0.9333 2.5241] [ -1.2904 -0.9333 2.5241]
[ 1.1850 0.5080 -1.3684] [ 1.1850 0.5080 -1.3684] [ 1.1850 0.5080 -1.3684]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.611945e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 39 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 5.9670 -7.3583 -7.6501] [ -0.5672 0.4078 -0.7155] [ 1.8322 0.0000 0.0000] [ 9.6519 7.5065 -34.9278]
[ 8.8602 4.4545 2.8144] * [ -0.6499 -0.7553 0.0847] * [ 0.0000 1.8460 0.0000] = [ -17.1201 3.1245 -13.7384]
[ 3.6743 -7.7929 -3.4237] [ -0.5059 0.5130 0.6934] [ 0.0000 0.0000 3.4251] [ 8.6343 10.3892 -19.3968]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 9.6519 7.5065 -34.9278] [ 9.6519 7.5065 -34.9278] [ 9.6519 7.5065 -34.9278]
[ -17.1201 3.1245 -13.7384] [ -17.1201 3.1245 -13.7384] [ -17.1201 3.1245 -13.7384]
[ 8.6343 10.3892 -19.3968] [ 8.6343 10.3892 -19.3968] [ 8.6343 10.3892 -19.3968]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 1.333974e-06
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
========================================================================================================================================
STAGE 40 VERIFICATION REPORT
Hardware DNA: 89ABCDEF 01234567 | User Key: 29F7C2D4 A3CBEDCB
----------------------------------------------------------------------------------------------------------------------------------------
MATRIX A MATRIX B MATRIX C FPGA RESULT (D)
[ 1.9588 -5.8794 -5.8865] [ -0.2738 0.1014 -0.9564] [ 0.4575 0.0000 0.0000] [ 3.3799 -1.4464 -2.2221]
[ 5.7873 -8.2667 -2.2346] * [ -0.7677 -0.6221 0.1538] * [ 0.0000 2.0266 0.0000] = [ 2.7707 8.0959 -3.8589]
[ -2.6469 5.4387 1.0356] [ -0.5794 0.7763 0.2482] [ 0.0000 0.0000 0.5242] [ -1.8531 -5.7715 1.9004]
PRECISION COMPARISON: FPGA vs REFERENCE MODELS
FPGA RESULT (Single) MATLAB REF (Float32) MATLAB REF (Double)
[ 3.3799 -1.4464 -2.2221] [ 3.3799 -1.4464 -2.2221] [ 3.3799 -1.4464 -2.2221]
[ 2.7707 8.0959 -3.8589] [ 2.7707 8.0959 -3.8589] [ 2.7707 8.0959 -3.8589]
[ -1.8531 -5.7715 1.9004] [ -1.8531 -5.7715 1.9004] [ -1.8531 -5.7715 1.9004]
----------------------------------------------------------------------------------------------------------------------------------------
LOGIC ACCURACY (vs Single): 0.000000e+00 | SCIENTIFIC DRIFT (vs Double): 3.290167e-07
STATUS: PASS (The hardware matches the IEEE-754 Single Precision model exactly)
========================================================================================================================================
Licensing & Ordering Information
ACE800333 is delivered as a pre‑packaged Vivado IP core, ready for integration through the AMD/Xilinx IP Catalog.
Each licensed core includes:
Pre‑packaged Vivado IP (compatible with IP Catalog) including simulation model
Memory map documentation (available in this datasheet)
USER_KEY file for license activation
Example project for rapid integration
ACE provides a USER_KEY value (64 bits) for FPGA Serial Number (DNA for AMD/Xilinx).
The keys are delivered in a simple csv file (a template is reported below):
DNA_HEX,AUTHORIZATION_KEY
0011223344556677,C303E222F7D44C5B
ABCDE1234567890F,A2A3A3114194ED74
5566778899AABBCC,94C023F594AA6F63
DEADBEEF12345678,F40237F85DFB6F2A
00123456789ABCDE,E8ACBBDBFCF3ACB7
...............,.................
The user may store the file with all the SN/licenses and select the key to load after reading the SN of the FPGA from the BRAM_PORTA interface of the ACE800333 core.
The envisioned process is the following:
The file with the keys is embedded the customer software
The customer software, waiting at least 5000 ns from power on, reads the FPGA SN from the BRAM_PORTA interface exposed by the ACE800333 core.
The customer software retrieves the USER_KEY corresponding to the FPGA SN in the ACE provided USER_KEY file.
The customer software loads the USER_KEY via the BRAM_PORTA interface exposed by the ACE800333 core.
The keys are generated on customer order.
In simulation, a demo DNA is used and the corresponding USER_KEY is provided in the file for a seamless experience.
Pricing is provided directly by ACE based on:
Deployment volume
License type
Optional customization requirements
Target FPGA family
Customers may request a quotation by providing their expected deployment profile and FPGA device list.
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