QR Givens 4x4 Inverter- ACE801044

Overview

The ACE801044 is a high-velocity, deterministic hardware accelerator designed for the real-time execution of QR Givens 4x4 matrix inversion algorithm. It provides a production-ready "Math-to-Silicon" pipeline that transforms complex mathematics into high-frequency, bit-perfect FPGA logic.

By offloading recursive mathematical kernels from a system’s primary processor, the core enables extreme computational throughput with zero execution jitter.

With its 180K operations per second, the ACE801044 may be used in real time systems avoiding the need to transfer back and forth data between hardware and software.

The core is engineered as a universal mathematical fabric for high-stakes environments. It is specifically optimized for:

Extended Kalman Filters (EKF): EKFs are the backbone of robot localization, target tracking, and state estimation. The correction step inherently requires inverting a measurement covariance or innovation matrix. Utilizing QR decomposition via Givens rotations provides superior numerical stability over Cholesky decomposition, preventing divergence in fixed-point hardware. A 4x4 matrix perfectly maps to tracking 4-dimensional states, such as 3D position plus time (x, y, z, t for GPS/GNSS receivers) or quaternion-based orientation components.
Model Predictive Control (MPC): Small-scale MPC controllers optimize a vehicle's trajectory on the fly. By leveraging a highly parallelized Givens rotation fabric, the core allows these constrained optimization loops to solve the underlying least-squares or quadratic programming problems at kilohertz rates on small, power-efficient edge FPGAs.
Inertial Navigation Systems (INS) and Attitude Heading Reference Systems (AHRS): Combining GPS data with IMU (Inertial Measurement Unit) data requires constant state updating. A 4x4 matrix inverter is ideal for processing standard 4-element quaternion orientations or 4D space-time kinematic states. The deterministic, microsecond-grade execution time guarantees that the critical navigation loop runs reliably well above 100 kHz.

The ACE801044 maintains a surprisingly lean resource utilization footprint that enables its implementation on the majority of the FPGA models.

The core is optimized for the AMD 7 Series FPGA, but ACE can easily port on any customer-selected FPGA (any vendor).

While the core is fully functional, ACE internal development procedures provide the possibility for the customer to adapt to their needs:

Matrix size
The FPGA model
Memory map
Core interfaces (e.g. the BRAM interfaces can be set to be controlled by an AXI BRAM Controller)

In contrast to software‑based implementations, the ACE801044 delivers architectural guarantees that general‑purpose processors cannot provide. By keeping all data resident inside the FPGA fabric, the core eliminates cache effects, DMA transfers, driver overhead, and any latency associated with moving data between hardware and software. This locality ensures that every execution follows the exact same timing path, resulting in strictly deterministic, jitter‑free behavior essential for real‑time control loops. Offloading the recursive kernel to dedicated logic also removes the most timing‑sensitive workload from the system processor, improving overall system parallelism and reducing power consumption by avoiding CPU burst activity.

Adopting the ACE801044 also accelerates development cycles by replacing months of low‑level mathematical implementation and numerical‑stability validation with a ready‑to‑use, fully verified hardware math engine. Instead of designing, debugging, and stress‑testing a custom inverter, engineering teams can integrate a proven, production‑grade core and focus their efforts on higher‑level system architecture. This reduces project risk, shortens time‑to‑deployment, and provides a measurable competitive advantage in markets where reliability, determinism, and rapid iteration are critical.

Key Features

Deterministic 1384 cycles Latency
Tested Clock Frequency: 250 MHz (timing closed with ample margin)
More than 180K operations per second at the tested frequency
Utilization: 3.5% of the resources on a mid-range xc7k160tfbg484-3
Portable across FPGA families and vendors.
BRAM-based control interface

Theory of operation

The ACE801044 is a high-performance, deterministic hardware acceleration engine designed to invert 4×4 matrices by means of the QR Givens decomposition.

To guarantee minimal, deterministic latency, the engine avoids iterative relaxation methods and instead utilizes a direct solver architecture split into three highly pipelined, single-precision floating-point (IEEE-754 float32) computational phases:

1. QR Decomposition

The engine computes the QR factorization of the input 4×4 matrix A, decomposing it into an orthogonal matrix Q and an upper triangular matrix R, such that:

A = Q × R

This factorization is achieved through a sequence of 6 distinct Givens rotations designed to systematically annihilate the lower triangular entries of the input matrix.

Each rotation operates on a specific plane to clear an off-diagonal element (a₁₀, a₂₀, a₃₀, r₂₁ᵛ¹, r₃₁ᵛ¹, r₃₂ᵛ²) while updating the affected rows.

The trigonometric rotation factors (cosine cₙ and sine sₙ) are evaluated inline using pipelined floating-point square root and division components to establish the norm for each rotation plane:

Norm and Vector Primitives: Computed using a pipelined multiply-accumulate (MAC) reduction chain followed by a square root.
Rotation Parameters: Evaluated via direct division of the diagnostic tracking elements, mapping the trigonometric plane precisely into the upper triangular matrix space.

2. Backward Substitution

Once the upper triangular matrix R is completely resolved, the engine determines its direct inverse (R⁻¹) by executing an inline backward substitution sweep. Because R is an upper triangular structure, the entries of X = R⁻¹ are solved in reverse order starting from the bottom-most scalar entry up to the top row:

Diagonal Inverse Entries: Resolved using an inline single-precision floating-point division primitive:
xₙₙ = 1 / rₙₙ
Off-Diagonal Inverse Entries: Computed row-by-row via pipelined multiply-accumulate chains that track the preceding resolved elements, isolating the definitive upper triangular inverse elements.

3. Final Inverse

The definitive matrix inverse A⁻¹ is synthesized by mapping the upper triangular inverse R⁻¹ back through the transposed orthogonal rotation matrices. To satisfy matrix transpose laws, the calculation progresses backward through the rotation sequence, propagating the values from the final rotation down to the first:

inv(A) = R⁻¹ × Q₆ × Q₅ × Q₄ × Q₃ × Q₂ × Q₁

The engine sequentially rotates the columns of the intermediate product matrices utilizing the previously calculated rotation factors (cₙ, sₙ). Because these operations are entirely unrolled and mapped onto dedicated, deterministic pipelined floating-point primitives, the runtime execution path is strictly bounded and entirely free from timing jitter.

The ACE801044 core utilizes IEEE-754 Single-Precision (32-bit) floating-point arithmetic.

The equivalent software implementation is reported below:

function ai = ace801044_inverse(A)

% ACE801044_INVERSE Self-contained mathematical reference model for the

% ACE801044 4x4 Givens QR Matrix Inversion Core.

% Unpack input matrix components into standalone scalar producers

a00 = A(1,1); a01 = A(1,2); a02 = A(1,3); a03 = A(1,4);

a10 = A(2,1); a11 = A(2,2); a12 = A(2,3); a13 = A(2,4);

a20 = A(3,1); a21 = A(3,2); a22 = A(3,3); a23 = A(3,4);

a30 = A(4,1); a31 = A(4,2); a32 = A(4,3); a33 = A(4,4);

% System constants

ONE = 1.0;

% =========================================================================

% --- 1. QR DECOMPOSITION (ALL ROTATIONS) ---

% =========================================================================

% Rot 1 (A10 -> 0)

norm1 = sqrt((a00 * a00) + (a10 * a10));

c1 = a00 / norm1;

s1 = (-a10) / norm1;

r00_v1 = (c1 * a00) - (s1 * a10);

r01_v1 = (c1 * a01) - (s1 * a11);

r02_v1 = (c1 * a02) - (s1 * a12);

r03_v1 = (c1 * a03) - (s1 * a13);

r11_v1 = (s1 * a01) + (c1 * a11);

r12_v1 = (s1 * a02) + (c1 * a12);

r13_v1 = (s1 * a03) + (c1 * a13);

% Rot 2 (A20 -> 0)

norm2 = sqrt((r00_v1 * r00_v1) + (a20 * a20));

c2 = r00_v1 / norm2;

s2 = (-a20) / norm2;

r00_v2 = (c2 * r00_v1) - (s2 * a20);

r01_v2 = (c2 * r01_v1) - (s2 * a21);

r02_v2 = (c2 * r02_v1) - (s2 * a22);

r03_v2 = (c2 * r03_v1) - (s2 * a23);

r21_v1 = (s2 * r01_v1) + (c2 * a21);

r22_v1 = (s2 * r02_v1) + (c2 * a22);

r23_v1 = (s2 * r03_v1) + (c2 * a23);

% Rot 3 (A30 -> 0)

norm3 = sqrt((r00_v2 * r00_v2) + (a30 * a30));

c3 = r00_v2 / norm3;

s3 = (-a30) / norm3;

r00 = (c3 * r00_v2) - (s3 * a30);

r01 = (c3 * r01_v2) - (s3 * a31);

r02 = (c3 * r02_v2) - (s3 * a32);

r03 = (c3 * r03_v2) - (s3 * a33);

r31_v1 = (s3 * r01_v2) + (c3 * a31);

r32_v1 = (s3 * r02_v2) + (c3 * a32);

r33_v1 = (s3 * r03_v2) + (c3 * a33);

% Rot 4 (r21_v1 -> 0)

norm4 = sqrt((r11_v1 * r11_v1) + (r21_v1 * r21_v1));

c4 = r11_v1 / norm4;

s4 = (-r21_v1) / norm4;

r11_v2 = (c4 * r11_v1) - (s4 * r21_v1);

r12_v2 = (c4 * r12_v1) - (s4 * r22_v1);

r13_v2 = (c4 * r13_v1) - (s4 * r23_v1);

r22_v2 = (s4 * r12_v1) + (c4 * r22_v1);

r23_v2 = (s4 * r13_v1) + (c4 * r23_v1);

% Rot 5 (r31_v1 -> 0)

norm5 = sqrt((r11_v2 * r11_v2) + (r31_v1 * r31_v1));

c5 = r11_v2 / norm5;

s5 = (-r31_v1) / norm5;

r11 = (c5 * r11_v2) - (s5 * r31_v1);

r12 = (c5 * r12_v2) - (s5 * r32_v1);

r13 = (c5 * r13_v2) - (s5 * r33_v1);

r32_v2 = (s5 * r12_v2) + (c5 * r32_v1);

r33_v2 = (s5 * r13_v2) + (c5 * r33_v1);

% Rot 6 (r32_v2 -> 0)

norm6 = sqrt((r22_v2 * r22_v2) + (r32_v2 * r32_v2));

c6 = r22_v2 / norm6;

s6 = (-r32_v2) / norm6;

r22 = (c6 * r22_v2) - (s6 * r32_v2);

r23 = (c6 * r23_v2) - (s6 * r33_v2);

r33 = (s6 * r23_v2) + (c6 * r33_v2);

% =========================================================================

% --- 2. BACK-SUBSTITUTION (R_inv) ---

% =========================================================================

x33 = ONE / r33;

x22 = ONE / r22;

x11 = ONE / r11;

x00 = ONE / r00;

x23 = (-r23) * x33 * x22;

x12 = (-r12) * x22 * x11;

x13_t0 = (-r12) * x23;

x13_t1 = (-r13) * x33;

x13 = (x13_t0 + x13_t1) * x11;

x01 = (-r01) * x11 * x00;

x02_t0 = (-r01) * x12;

x02_t1 = (-r02) * x22;

x02 = (x02_t0 + x02_t1) * x00;

x03_t0 = (-r01) * x13;

x03_t1 = (-r02) * x23;

x03_t2 = (-r03) * x33;

x03 = (x03_t0 + x03_t1 + x03_t2) * x00;

% =========================================================================

% --- 3. FINAL INVERSE (A_inv) via Retrograde Right-Multiplication ---

% =========================================================================

% --- Step 3.1: Apply Q6 (Rotates Columns 2 and 3 using c6, s6) ---

g02_v1 = (c6 * x02) + (s6 * x03);

g03_v1 = -(s6 * x02) + (c6 * x03);

g12_v1 = (c6 * x12) + (s6 * x13);

g13_v1 = -(s6 * x12) + (c6 * x13);

g22_v1 = (c6 * x22) + (s6 * x23);

g23_v1 = -(s6 * x22) + (c6 * x23);

g32_v1 = s6 * x33;

g33_v1 = c6 * x33;

% --- Step 3.2: Apply Q5 (Rotates Columns 1 and 3 using c5, s5) ---

g01_v1 = (c5 * x01) + (s5 * g03_v1);

g03_v2 = -(s5 * x01) + (c5 * g03_v1);

g11_v1 = (c5 * x11) + (s5 * g13_v1);

g13_v2 = -(s5 * x11) + (c5 * g13_v1);

g21_v1 = s5 * g23_v1;

g23_v2 = c5 * g23_v1;

g31_v1 = s5 * g33_v1;

g33_v2 = c5 * g33_v1;

% --- Step 3.3: Apply Q4 (Rotates Columns 1 and 2 using c4, s4) ---

g01_v2 = (c4 * g01_v1) + (s4 * g02_v1);

g02_v2 = -(s4 * g01_v1) + (c4 * g02_v1);

g11_v2 = (c4 * g11_v1) + (s4 * g12_v1);

g12_v2 = -(s4 * g11_v1) + (c4 * g12_v1);

g21_v2 = (c4 * g21_v1) + (s4 * g22_v1);

g22_v2 = -(s4 * g21_v1) + (c4 * g22_v1);

g31_v2 = (c4 * g31_v1) + (s4 * g32_v1);

g32_v2 = -(s4 * g31_v1) + (c4 * g32_v1);

% --- Step 3.4: Apply Q3 (Rotates Columns 0 and 3 using c3, s3) ---

g00_v1 = (c3 * x00) + (s3 * g03_v2);

ai03 = -(s3 * x00) + (c3 * g03_v2);

g10_v1 = s3 * g13_v2;

ai13 = c3 * g13_v2;

g20_v1 = s3 * g23_v2;

ai23 = c3 * g23_v2;

g30_v1 = s3 * g33_v2;

ai33 = c3 * g33_v2;

% --- Step 3.5: Apply Q2 (Rotates Columns 0 and 2 using c2, s2) ---

g00_v2 = (c2 * g00_v1) + (s2 * g02_v2);

ai02 = -(s2 * g00_v1) + (c2 * g02_v2);

g10_v2 = (c2 * g10_v1) + (s2 * g12_v2);

ai12 = -(s2 * g10_v1) + (c2 * g12_v2);

g20_v2 = (c2 * g20_v1) + (s2 * g22_v2);

ai22 = -(s2 * g20_v1) + (c2 * g22_v2);

g30_v2 = (c2 * g30_v1) + (s2 * g32_v2);

ai32 = -(s2 * g30_v1) + (c2 * g32_v2);

% --- Step 3.6: Apply Q1 (Rotates Columns 0 and 1 using c1, s1) ---

ai00 = (c1 * g00_v2) + (s1 * g01_v2);

ai01 = -(s1 * g00_v2) + (c1 * g01_v2);

ai10 = (c1 * g10_v2) + (s1 * g11_v2);

ai11 = -(s1 * g10_v2) + (c1 * g11_v2);

ai20 = (c1 * g20_v2) + (s1 * g21_v2);

ai21 = -(s1 * g20_v2) + (c1 * g21_v2);

ai30 = (c1 * g30_v2) + (s1 * g31_v2);

ai31 = -(s1 * g30_v2) + (c1 * g31_v2);

% Pack back into an explicit 4x4 matrix result

ai = [ ai00, ai01, ai02, ai03;

ai10, ai11, ai12, ai13;

ai20, ai21, ai22, ai23;

ai30, ai31, ai32, ai33 ];

end

Detailed Resource Utilization

The data below are representative of the AMD 7 series architecture. The percentage are relative to the budget friendly xc7k160tfbg484-3 .

Used CLB LUTs: 3559 (3.55%)
- LUT as logic: 3465
- LUT as Shift Registers: 94
CLB Registers: 4092 (2.02%)
CARRY4: 378
F7 Muxes:199
F8 Muxes: 78
CLB Tiles (in the verification project): 1170 (4.62%)
Used DSP: 5 (0.83%)
Used BRAM36K: 1 (0.31%)
Used BRAM18K: 0 (0.00%)
DNA PORT: 1

Timing and throughput

The core runs on two different clocks:

CLK_FAST with a maximum frequency of 250 MHz
CLK_SLOW that shall run at 50MHz (phase aligned with CLK_FAST)

CLK_SLOW is used for the ACE801044 initialization, while CLK_FAST is used for all the runtime operations.

In the verification project, the timing was closed with a robust 0.755ns timing margin and with 0 timing violations.

Interfaces and operation flow

The QR Givens 4x4 Inverter core is packaged as an AMD IP core. Figure 1 illustrates the verification configuration.

Figure 1

The core is fully controlled through read/write operations on a BRAM (optionally accessible via an AXI BRAM_CONTROLLER). The instantiated BRAM is 1 True Dual Port with port A available to the user and port B managed by the internal Math Engine.

The BRAM has a width of 32 bits and a depth of 1024 locations. The core uses the first 128 locations, with the remaining ones completely available for the user via port(s) A (port(s) B are assigned to the internal Math Engine). Port(s) A operates in the user clock domain; Port(s) B operates in the internal engine clock domain.

The memory Map is reported below:

Memory Map

ACE801044 Core Memory Map V2

In addition to the BRAM interface, the core exposes:

Two clock slave interfaces:
- CLK_SLOW is used for the initialization and for the access to the DNA reader primitive ( 50MHz)
- CLK_FAST is used to drive the internal computation engine (Max Frequency: 250 MHz)
A BUSY pin that, when set to high, signals when the core is executing the initialization or its main function.

The core, at power-up, performs an initialization sequence that lasts (with CLK_SLOW @ 50 MHz) less than 5000 ns.

When the initialization is complete, the BRAM is populated with the DNA of the FPGA (see Memory Map).

Once the initialization is complete, the user may load the BRAM in accordance with the input reported in the Memory Map and,finally, set the START_CMD to 0x1.

The results are written in BRAM, in accordance with the memory map, after exactly 1384 clock cycles (5.536 s @ 250 MHz) . The end of execution is communicated by the core by setting the START_CMD to 0x0 (in BRAM) and via the BUSY PIN (BUSY=0 indicates the core is in the IDLE state, ready for the new execution).

When the START_CMD is asserted, the core performs the entire computation. Execution cannot be stopped. Writing on the BRAM first 128 addresses during the execution will produce undefined results and it is not supported. The execution will always complete in the specified 1384 clock cycle window.

Note: if the USER_KEY is not correct, the core terminates in the specified timeframe, but produces unpredictable results.

Results and accuracy

To validate the numerical integrity and dynamic range stability of the ACE801044 computing fabric, the hardware engine was subjected to a rigorous, 10-stage hardware-in-the-loop simulation test sweep. The verification manifest intentionally sweeps the input matrix (A) across diverse operational ranges, forcing the internal single-precision floating-point (float32) pipelines to calculate direct matrix inversions under varying conditioning states.

Testing was evaluated against an unconditioned double-precision analytical software baseline model utilizing maximum observed epsilon drift bounds to audit precision degradation. A strict verification threshold was enforced to guarantee algorithmic convergence stability near matrix singularities and prevent catastrophic cancellation during the back-multiplication and retrograde column-rotation phases.

As compiled in the hardware bit-fidelity verification report below, the core achieved 100% numerical equivalence with zero precision breaches across all evaluated operating envelopes:

Maximum Epsilon Drift: Successfully bounded in the sub-fractional nano-signal space, peaking at 3.541629 × 10⁻⁸ under peak stress loading (Stage 6).
Nominal Tracking Bounds: Routinely converged well below 1.2 × 10⁻⁸ drift (Stage 2), demonstrating true IEEE-754 bit-perfect math propagation.

=========================================================

ACE801044 BIT-FIDELITY VERIFICATION REPORT

=========================================================

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_1

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 2.411946e-08

Original Input Matrix (A):

5.5377 0.3188 3.5784 0.7254

1.8339 -6.3077 2.7694 -0.0631

-2.2588 -0.4336 -6.3499 0.7147

0.8622 0.3426 3.0349 -5.2050

Hardware Computed Matrix Inverse (A^-1):

0.2365 0.0039 0.1613 0.0551

0.0305 -0.1536 -0.0502 -0.0008

-0.0873 0.0086 -0.2235 -0.0430

-0.0097 -0.0044 -0.1069 -0.2081

Golden Model Analytical Matrix Inverse:

0.2365 0.0039 0.1613 0.0551

0.0305 -0.1536 -0.0502 -0.0008

-0.0873 0.0086 -0.2235 -0.0430

-0.0097 -0.0044 -0.1069 -0.2081

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_2

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 1.189276e-08

Original Input Matrix (A):

-5.1241 0.6715 0.4889 0.2939

1.4897 -6.2075 1.0347 -0.7873

1.4090 0.7172 5.7269 0.8884

1.4172 1.6302 -0.3034 -6.1471

Hardware Computed Matrix Inverse (A^-1):

-0.1965 -0.0200 0.0202 -0.0039

-0.0299 -0.1546 0.0317 0.0230

0.0608 0.0316 0.1649 0.0227

-0.0562 -0.0472 0.0049 -0.1586

Golden Model Analytical Matrix Inverse:

-0.1965 -0.0200 0.0202 -0.0039

-0.0299 -0.1546 0.0317 0.0230

0.0608 0.0316 0.1649 0.0227

-0.0562 -0.0472 0.0049 -0.1586

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_3

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 1.885660e-08

Original Input Matrix (A):

-6.0689 0.3252 -0.1022 -0.8649

-0.8095 -5.7549 -0.2414 -0.0301

-2.9443 1.3703 5.3192 -0.1649

1.4384 -1.7115 0.3129 5.6277

Hardware Computed Matrix Inverse (A^-1):

-0.1698 -0.0022 -0.0018 -0.0262

0.0278 -0.1749 -0.0076 0.0031

-0.0994 0.0421 0.1886 -0.0095

0.0574 -0.0550 -0.0123 0.1859

Golden Model Analytical Matrix Inverse:

-0.1698 -0.0022 -0.0018 -0.0262

0.0278 -0.1749 -0.0076 0.0031

-0.0994 0.0421 0.1886 -0.0095

0.0574 -0.0550 -0.0123 0.1859

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_4

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 1.630070e-08

Original Input Matrix (A):

6.0933 -1.2141 -0.7697 -1.0891

1.1093 -6.1135 0.3714 0.0326

-0.8637 -0.0068 -5.2256 0.5525

0.0774 1.5326 1.1174 6.1006

Hardware Computed Matrix Inverse (A^-1):

0.1655 -0.0250 -0.0194 0.0314

0.0283 -0.1674 -0.0145 0.0073

-0.0278 0.0087 -0.1842 0.0117

-0.0041 0.0408 0.0376 0.1596

Golden Model Analytical Matrix Inverse:

0.1655 -0.0250 -0.0194 0.0314

0.0283 -0.1674 -0.0145 0.0073

-0.0278 0.0087 -0.1842 0.0117

-0.0041 0.0408 0.0376 0.1596

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_5

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 2.370018e-08

Original Input Matrix (A):

6.5442 -1.0616 -0.1924 -1.4224

0.0859 7.3505 0.8886 0.4882

-1.4916 -0.6156 -5.7648 -0.1774

-0.7423 0.7481 -1.4023 -5.1961

Hardware Computed Matrix Inverse (A^-1):

0.1500 0.0263 0.0085 -0.0389

0.0036 0.1370 0.0183 0.0112

-0.0389 -0.0221 -0.1791 0.0147

-0.0104 0.0219 0.0498 -0.1892

Golden Model Analytical Matrix Inverse:

0.1500 0.0263 0.0085 -0.0389

0.0036 0.1370 0.0183 0.0112

-0.0389 -0.0221 -0.1791 0.0147

-0.0104 0.0219 0.0498 -0.1892

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_6

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 3.541629e-08

Original Input Matrix (A):

6.4193 -0.8045 0.2157 0.7223

0.2916 5.6966 -1.1658 2.5855

0.1978 0.8351 -6.1480 -0.6669

1.5877 -0.2437 0.1049 5.1873

Hardware Computed Matrix Inverse (A^-1):

0.1630 0.0214 0.0011 -0.0332

0.0167 0.1789 -0.0350 -0.0960

0.0129 0.0248 -0.1675 -0.0357

-0.0494 0.0013 0.0014 0.1992

Golden Model Analytical Matrix Inverse:

0.1630 0.0214 0.0011 -0.0332

0.0167 0.1789 -0.0350 -0.0960

0.0129 0.0248 -0.1675 -0.0357

-0.0494 0.0013 0.0014 0.1992

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_7

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 3.021334e-08

Original Input Matrix (A):

-5.0825 0.8404 0.3035 1.7119

-1.9330 -5.8880 -0.6003 -0.1941

-0.4390 0.1001 5.4900 -2.1384

-1.7947 -0.5445 0.7394 -5.8396

Hardware Computed Matrix Inverse (A^-1):

-0.1713 -0.0191 0.0148 -0.0550

0.0543 -0.1654 -0.0252 0.0306

0.0041 0.0103 0.1924 -0.0696

0.0481 0.0226 0.0222 -0.1660

Golden Model Analytical Matrix Inverse:

-0.1713 -0.0191 0.0148 -0.0550

0.0543 -0.1654 -0.0252 0.0306

0.0041 0.0103 0.1924 -0.0696

0.0481 0.0226 0.0222 -0.1660

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_8

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 2.673986e-08

Original Input Matrix (A):

6.3546 1.4367 2.9080 -0.4686

-1.0722 -6.9609 0.8252 -0.2725

0.9610 -0.1977 6.3790 1.0984

0.1240 -1.2078 -1.0582 -5.2779

Hardware Computed Matrix Inverse (A^-1):

0.1802 0.0465 -0.0945 -0.0381

-0.0322 -0.1546 0.0378 0.0187

-0.0312 -0.0187 0.1803 0.0413

0.0179 0.0402 -0.0470 -0.2029

Golden Model Analytical Matrix Inverse:

0.1802 0.0465 -0.0945 -0.0381

-0.0322 -0.1546 0.0378 0.0187

-0.0312 -0.0187 0.1803 0.0413

0.0179 0.0402 -0.0470 -0.2029

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_9

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 2.510272e-08

Original Input Matrix (A):

5.7015 -1.5771 -1.3337 0.0229

-2.0518 5.5080 1.1275 -0.2620

-0.3539 0.2820 5.3502 -1.7502

-0.8236 0.0335 -0.2991 -5.2857

Hardware Computed Matrix Inverse (A^-1):

0.1951 0.0541 0.0365 -0.0139

0.0714 0.2033 -0.0251 -0.0014

-0.0006 -0.0093 0.1853 -0.0609

-0.0299 -0.0066 -0.0163 -0.1836

Golden Model Analytical Matrix Inverse:

0.1951 0.0541 0.0365 -0.0139

0.0714 0.2033 -0.0251 -0.0014

-0.0006 -0.0093 0.1853 -0.0609

-0.0299 -0.0066 -0.0163 -0.1836

---------------------------------------------------------

EVALUATION RESULTS FOR: STAGE_10

---------------------------------------------------------

VERDICT: [PASS]

Maximum Observed Epsilon Drift: 2.309516e-08

Original Input Matrix (A):

-5.8314 -2.0026 -0.0348 -0.7145

-0.9792 5.9642 -0.7982 1.3514

-1.1564 0.5201 6.0187 -0.2248

-0.5336 -0.0200 -0.1332 -5.5890

Hardware Computed Matrix Inverse (A^-1):

-0.1617 -0.0536 -0.0079 0.0080

-0.0339 0.1546 0.0212 0.0409

-0.0275 -0.0235 0.1627 -0.0087

0.0162 0.0051 -0.0032 -0.1796

Golden Model Analytical Matrix Inverse:

-0.1617 -0.0536 -0.0079 0.0080

-0.0339 0.1546 0.0212 0.0409

-0.0275 -0.0235 0.1627 -0.0087

0.0162 0.0051 -0.0032 -0.1796

=========================================================

FINAL REPORT: SUCCESS (All stages match within verification limit)

=========================================================

Licensing & Ordering Information

ACE801044 is delivered as a pre‑packaged Vivado IP core, ready for integration through the AMD/Xilinx IP Catalog.

Each licensed core includes:

Pre‑packaged Vivado IP (compatible with IP Catalog) including simulation model
Memory map documentation (available in this datasheet)
USER_KEY file for license activation
Example project for rapid integration

ACE provides a USER_KEY value (64 bits) for FPGA Serial Number (DNA for AMD/Xilinx).

The keys are delivered in a simple csv file (a template is reported below):

DNA_HEX,AUTHORIZATION_KEY

0011223344556677,C303E222F7D44C5B

ABCDE1234567890F,A2A3A3114194ED74

5566778899AABBCC,94C023F594AA6F63

DEADBEEF12345678,F40237F85DFB6F2A

00123456789ABCDE,E8ACBBDBFCF3ACB7

...............,.................

The user may store the file with all the SN/licenses and select the key to load after reading the SN of the FPGA from the BRAM_PORTA interface of the ACE801044 core.

The envisioned process is the following:

The file with the keys is embedded the customer software
The customer software, waiting at least 5000 ns from power on, reads the FPGA SN from the BRAM_PORTA interface exposed by the ACE801044 core.
The customer software retrieves the USER_KEY corresponding to the FPGA SN in the ACE provided USER_KEY file.
The customer software loads the USER_KEY via the BRAM_PORTA interface exposed by the ACE801044 core.

The keys are generated on customer order.

In simulation, a demo DNA is used and the corresponding USER_KEY is provided in the file for a seamless experience.

Pricing is provided directly by ACE based on:

Deployment volume
License type
Optional customization requirements
Target FPGA family

Customers may request a quotation by providing their expected deployment profile and FPGA device list.