Neural ACE Motion Control & Dynamic Friction Compensation Accelerator - ACE910N01 Datasheet 

Overview

The ACE910N01 is an ultra-fast, deterministic hardware co-processor engineered by Accelerated Computing Engineering (ACE) for real-time motion control, precision servo actuation, and dynamic non-linear friction compensation. Operating as a production-ready "Math-to-Silicon" architecture, the IP core offloads complex kinematics, multi-variable non-linear disturbance compensation, and field-oriented control (FOC) vector loops directly into high-speed, cycle-accurate FPGA hardware.

Non-linear mechanical friction—specifically velocity-reversal stiction, the Stribeck effect, viscous dissipation, and acceleration-dependent thermal hysteresis—represents the single largest impediment to tracking precision and tactile transparency in high-performance drive systems. 

While classical PID and static feedforward look-up tables struggle to adapt across dynamic velocity reversals and shifting thermal operating points, the ACE910N01 integrates the proprietary Neural ACE artificial neural network engine. Running in parallel with IEEE-754 single-precision floating-point arithmetic and high-bandwidth CORDIC vector engines, Neural ACE synthesizes an optimal feedforward counter-torque in lockstep with the current-loop update. 

ACE910N01 is controlled via dual RAM based interfaces (port 1 for the controlling logic and port 2 for the core itself), making it easy to integrate and avoid complex cross-clock domains.

Targeted for Advanced Robotics, Semiconductor Lithography, Medical Teleoperation, and High-Precision Machine Tools, the ACE910N01 delivers deterministic microsecond-grade execution with an ultra-lean silicon footprint.

More information about customization and product development can be found at www.accelerated-computing.be

Key features

• Deterministic 2,450-Cycle Real-Time Latency: Fixed 12.250 µs execution at 200 MHz with zero execution jitter, regardless of dynamic trajectories or temperature shifts.

• High Loop Bandwidth: Up to 81.63 kHz continuous pipeline throughput capacity, providing a 75.5% timing margin inside standard 20 kHz (50 µs) field-oriented control periods.

• 96.6% Dynamic Friction Error Elimination: Reduces global physical torque error from 0.2409 Nm to 0.0081 Nm on a 2.50 Nm full-scale system (residual error of only 0.32% FSR).

• Zero-Velocity Stiction Cancellation: Reduces breakaway zone error (|v| ≤ 1.5 rad/s) from 0.2532 Nm down to 0.0168 Nm (+0.2364 Nm net torque improvement).

• Configurable Neural ACE On-Chip Memory: Includes an independent AXI/LMB accessible microcode memory allowing runtime flashing and reconfiguration of custom neural network topologies and weights.

• Decoupled Silicon Footprint vs. Network Depth: Network topology and parameter count scale execution latency, not FPGA logic or DSP resources.

• Turnkey Model-to-Silicon Toolchain: Scope of delivery includes an automated GUI executable and a Python library for Quantization-Aware Training (QAT), coupled with ACE Cloud Compilation Services for one-click microcode binary generation.

• Minimal Silicon Footprint: Requires only ~11% Slice LUTs (6,984) and 5% DSP48E1 slices (12) on an entry-level AMD Artix-7 xc7a100tcsg324-1 FPGA, leaving ~89% of the device available for multi-axis drive logic and communications.

• Hardware-Tethered Security: Cryptographically locked and validated via FPGA Silicon DNA binding.

Functional Description & Control Formulation 

The ACE910N01 executes an end-to-end motion control pipeline consisting of three stages: Kinematics & Signal Conditioning (Phase A), Neural ACE Feedforward Synthesis, and FOC Current Control & Space-Vector Duty Generation (Phase B). 

High-Level Functional Flow

To ensure bit-exact parity with the FPGA silicon implementation, the executable Python software twin mirrors the complete ACE910N01 hardware execution pipeline for verification, latency profiling, and system-level integration.

Input Quantization & Format Specifications 

To provide seamless integration with standard motor control ADCs and encoders, the ACE910N01 accepts inputs in industry-standard formats. All input bit-widths, scaling gains, and zero-offset alignments can be fully customized upon request.

• Rotor Position (theta_curr_fx): 32-bit signed 2Q30 scaled radians ([-1.0, +1.0) corresponding to [-π, +π)). Compatible with optical encoders, magnetic resolvers, and BiSS-C/EnDat digital interfaces.

• Phase Currents & Temperature (I_a_raw, I_b_raw, temp_raw): 16-bit signed integer ADC counts shifted to Bit-30 MSB alignment (15-bit left shift). Configurable to direct 12-bit, 16-bit, or 18-bit delta-sigma conversions.

• Target Velocity (target_vel): IEEE-754 single-precision float (rad/s).

• Space-Vector PWM Outputs (duty_alpha, duty_beta): 32-bit unsigned 2Q30 normalized duty ratios (0 to 2^30), easily converted to 16-bit PWM timer registers via a 15-bit right shift.

Neural ACE: Architecture, Training & Cloud Toolchain 

Neural Architecture & Parameter Scaling 

The pre-compiled reference design implements an 8-layer deep Quantized Artificial Neural Network (QANN) with the following structure:

• Network Inputs (3): Normalized Velocity (v_norm), Filtered Acceleration (a_norm), Ambient Temperature (temp_norm).

• Network Output (1): Feedforward Counter-Torque (T_ff).

• Topology: 3 → 36 → 36 → 72 → 36 → 21 → 18 → 15 → 1.

• Total Parameter Count: 7,816 parameters (7,617 weights + 199 biases), quantized to INT8 precision.

Critical Silicon Decoupling: NeuralACE hardware is a runtime programmable engine. The physical FPGA resource utilization (LUTs, registers, DSPs) remains strictly constant regardless of network depth or layer dimensions. Expanding or reducing the neural network modifies only the execution cycle latency and instruction count, leaving the FPGA silicon footprint completely unaffected.

Runtime Reconfigurable

The ACE910N01 features dedicated instruction memory blocks accessible via standard AXI/LMB memory-mapped buses during normal operation:

• INSTRUCTION RAM 01 : 32-bit Lower Instruction Word.

• INSTRUCTION RAM 02 : 32-bit Upper Instruction Word.

This allows host systems to flash new neural topologies, updated motor calibrations, or wear-compensated model weights online without interrupting base FPGA bitstream operation. The memory comfortably accommodates standard motor models (the 8-layer, 7,816-parameter reference design compiles into 1,457 instruction words).

Scope of delivery

Every ACE910N01 license includes a comprehensive software suite for rapid deployment:

1. Standalone QAT Training GUI Executable: A turnkey desktop tool allowing engineers to import experimental motor drive trajectories, define layer sizes, and execute automated Quantization-Aware Training (QAT).

2. Python / PyTorch Neural ACE Library: A full SDK for advanced machine learning teams to embed custom non-linear friction models, loss functions, and thermal models directly into existing training workflows.

3. ACE Cloud Conversion Portal: Secure compilation service that ingests trained PyTorch models (.pt) and outputs microcode binaries (.coe / .bin) tailored for direct flashing into the ACE910N01 instruction RAM.

Hardware Resource Utilization 

The resource utilization for the standalone ACE910N01 core (comprising the Math Engine, Neural ACE Co-processor, CORDIC trig unit, and floating-point primitives) placed on an AMD Artix-7 xc7a100tcsg324-1 is detailed below. Note: Reported utilization includes a MicroBlaze soft core and debug infrastructure used only for validation. The delivered ACE910N01 IP core (without MicroBlaze) consumes fewer resources than the figures shown 

The resource utilization for the standalone ACE910N01 core (comprising the Math Engine, Neural ACE Co-processor, CORDIC trig unit, and floating-point primitives) placed on an AMD Artix-7 xc7a100tcsg324-1 is detailed below. Note: Reported utilization includes a MicroBlaze soft core and debug infrastructure used only for validation. The delivered ACE910N01 IP core (without MicroBlaze) consumes fewer resources than the figures shown.

Slice LUTs: 6,984 / 63,400 (11.02%)

Slice Registers (Flip-Flops): 8,356 / 126,800 (6.59%)

Block RAM (Tiles): 11 / 135 (8.15%)

DSP48E1 Slice Primitives: 12 / 240 (5.00%)

Timing & Latency Specifications 

Engine Clock (CLK_FAST): 200.0 MHz — 5.0 ns period driving high-speed math logic

Execution Latency: 2,450 Cycles (12.250 µs) — Deterministic cycle count across all dynamic operating points

Execution Jitter: 0.000 ns — Zero-jitter pipeline execution

Max Continuous Throughput: 81.63 kHz — Allows execution within ultra-high-speed current loops

User Interface & Memory Map

The core is controlled through a dual-port memory-mapped interface. Only registers required for user configuration, command injection, and output duty retrieval are exposed below; internal scratchpads and intermediate registers are reserved.

• TRIGGER (Word 0 | 0x0000 | uint32): Core trigger: Write 0x01 to start execution; auto-cleared upon completion

• theta_curr_fx (Word 1 | 0x0004 | int32): Current electrical rotor position (2Q30 scaled radians: 1.0 = π)

• I_a_raw_fx (Word 3 | 0x000C | int32): Phase A current raw ADC count (<< 15 shifted)

• I_b_raw_fx (Word 4 | 0x0010 | int32): Phase B current raw ADC count (<< 15 shifted)

• temp_raw_fx (Word 5 | 0x0014 | int32): Temperature sensor raw ADC count (<< 15 shifted)

• target_vel (Word 6 | 0x0018 | float32): Target mechanical velocity command (rad/s)

• T_ff (Word 12 | 0x0030 | float32): Synthesized Neural ACE Feedforward Friction Torque (Nm)

• T_total (Word 13 | 0x0034 | float32): Total commanded torque (T_linear + T_ff) in Nm

• I_q_target (Word 14 | 0x0038 | float32): Target quadrature current command (A)

• duty_alpha_fx (Word 26 | 0x0068 | int32): Synthesized Space-Vector PWM Duty Alpha (2Q30 counts)

• duty_beta_fx (Word 27 | 0x006C | int32): Synthesized Space-Vector PWM Duty Beta (2Q30 counts)

• System Parameters (Words 30..44 | 0x0078 - 0x00B0 | float32): Physical motor and loop gains (Ts, V_max, A_max, Kt, Vdc, Kp, Ki, Kp_d, Ki_d...)

• Calibration Offsets (Words 45..49 | 0x00B4 - 0x00C4 | i32 / flt): ADC zero offsets and scale conversion gains

• RESERVED (Others | Various | —): Internal pipeline registers, integrators, and scratchpads

Note: While test and verification suites utilize an auxiliary soft-core processor (MicroBlaze) for telemetry, vector injection, and cycle-accurate latency profiling, this processor is strictly a test fixture and is not part of the final delivered silicon IP core. The standalone ACE910N01 core operates autonomously with native dual-port RAM interfaces. The interfaces may be controlled via Hard/Soft Processors (e.g., LMB or AXI) or pure RTL for "close to wire" designs.

Silicon Validation & Benchmark Performances

Physical hardware validation was conducted on the Artix-7 device across an automated 100-test matrix spanning velocity sweeps (-9.00 rad/s to +9.00 rad/s), temperatures (20.0 °C to 80.0 °C), and electrical angles (0.0° to 178.2°).

• Breakaway / Stiction (|v| <= 1.5 rad/s): Uncompensated Baseline: 0.2532 Nm | ACE910N01 Output: 0.0168 Nm | Net Accuracy Gain: +0.2364 Nm | Status: 100% PASS

• Nominal Domain (|v| > 1.5 rad/s): Uncompensated Baseline: 0.2386 Nm | ACE910N01 Output: 0.0064 Nm | Net Accuracy Gain: +0.2322 Nm | Status: 100% PASS

• Global 100-Test Average: Uncompensated Baseline: 0.2409 Nm | ACE910N01 Output: 0.0081 Nm | Net Accuracy Gain: +0.2329 Nm (+9.31% FSR) | Status: 100 / 100 PASS

Licensing & Deliverables

Delivered as an encrypted or RTL-level AMD Vivado IP core, the ACE910N01 package includes:

• ACE910N01 Hardware IP Core (VHDL netlist) with timing closure constraints.

• Standalone Model-to-Silicon QAT Training GUI Executable.

• Advanced Python / PyTorch QAT Training & Validation SDK.

• Access credentials to the ACE Cloud Microcode Compilation Portal.

• Bit-exact Python software twin reference test suite.

• Silicon DNA USER_KEY authorization file for IP licensing protection.

For evaluation kits, benchmark test vectors, or custom motor training engagements, contact Accelerated Computing Engineering (ACE).